LVDS Clock Buffer Layout And Termination Practice
A clock buffer that distributes one reference to four or more loads is judged by two numbers that a schematic cannot show: how much jitter it adds, and how far apart the outputs drift from each other. Both are decided largely by the layout. A part with excellent specifications can still produce a poor result if the differential pairs are routed carelessly or if the termination sits in the wrong place.
This article looks at an LVDS clock buffer used to fan out a 156.25 MHz reference to a PHY, an FPGA and a switch, and at the layout decisions that keep the additive jitter low and the output skew small. The same reasoning applies to any low voltage differential clock distribution on a dense board.
What The Buffer Has To Deliver
Three parameters frame the design. The additive jitter is the noise the buffer contributes on top of the reference, and it is quoted as an RMS phase value. The output skew is the difference in propagation delay between outputs of the same device, and the part to part skew is the difference between devices. The third is the output bandwidth, which must exceed the highest clock frequency the system uses with margin.
For a synchronous link, the number that matters most is the total skew against the unit interval. If four outputs arrive within a fraction of the UI, the receivers can sample without an extra phase calibration step, which removes a calibration routine and a source of field failures. When the skew budget is treated as a layout problem rather than a part specification, it is usually achievable.
Power Filtering For A Clock Device
A clock device draws a small current, often only a few tens of milliamps, but it draws it in narrow pulses that are synchronised with the output edges. Those pulses contain energy at the harmonics of the clock, and if the supply impedance is not low at those frequencies the noise modulates the output timing. The supply is therefore part of the jitter budget, not a housekeeping detail.
Place a small ceramic capacitor of about 0.1 microfarad in an 0402 body within two millimetres of the supply pin, and add a bulk capacitor of about 10 microfarads nearby. The small part handles the high frequency content and the larger part supplies the slower transients. Keep the return path short by placing the capacitor ground via next to the pin ground rather than at the far end of a trace.
Differential Pair Routing Rules
Each LVDS output pair should be routed as a controlled impedance pair, normally 100 ohms differential, with the two conductors held at a constant spacing. The intra pair skew should be kept under about 5 mil, because a mismatch turns part of the differential signal into a common mode component that radiates and reduces the eye opening. Length matching within the pair matters more than matching between pairs.
When several outputs must stay synchronous, match the lengths between the pairs as well. Route the pairs over a continuous reference plane, keep the spacing to other nets at least three times the trace width, and avoid layer changes. If a change is unavoidable, place the reference vias close to the signal vias so that the return current can follow. The techniques for turning differential traces and for matching lengths apply directly to a clock tree.
Where The Termination Resistor Goes
The 100 ohm termination belongs at the receiver, as close to the input pin as the layout allows. Placing it at the driver is a common shortcut and it produces the overshoot that a designer then tries to fix with a series component. With the resistor at the driver, the trace between the resistor and the receiver is unterminated, so the reflection returns to the source and appears as ringing on the edge.
With the resistor at the receiver, the trace is properly terminated along its length and the edge that arrives is clean. The difference is visible on an eye diagram immediately, and it costs nothing but a placement decision. Where a pair feeds two receivers, split the termination so that each branch is terminated at its own input rather than sharing one resistor at a branch point.
Input Compatibility And Single Ended Use
Many clock buffers accept several logic families at the input, which removes a level translator from the bill of materials. The datasheet lists which standards are supported directly, and the input bias network is usually built in. That internal bias is what makes a single ended drive possible: the complementary input is held at a reference near the middle of the input swing, and the signal is applied to the other pin.
If a single ended source is used, the reference must be clean, because any noise on it appears directly in the timing. A resistor divider from the supply is adequate only if the supply is quiet; otherwise derive the reference from a filtered source. Confirm the input common mode range from the datasheet before committing, since a source that sits outside the range will produce an output that looks correct on a slow scope and fails at temperature.
Thermal And Package Considerations
A clock buffer in a small package still has to shed its dissipation. The junction temperature is the ambient plus the power multiplied by the junction to ambient thermal resistance, and for a thin shrink small outline package that resistance is on the order of 138 degrees Celsius per watt. A device dissipating 0.165 watts in an 85 degree ambient therefore sits near 108 degrees, which is well inside the limit but not negligible.
The practical conclusion is that no heat sink is required, but the copper under the device should not be isolated from the rest of the board. A few square millimetres of copper connected to the ground plane gives the package somewhere to spread its heat. Where several clock devices sit together, keep them apart so that they do not share the same warm pocket of air.
Process Control and Verification
On a design of this kind, LVDS clock buffer is the item that decides how the rest of the board is arranged. A stack-up that is drawn rather than described removes most of the ambiguity from a quotation, and it lets the fabricator price the board against the dielectric and copper weights that will actually be used. Where the requirement is not written down, the shop supplies its own default, and the default is chosen for the process rather than for the design.
Related reading: our fabrication notes, board quality and design release notes cover the same ground.
FAQ
Should the differential pairs be length matched to each other or only within the pair? Match within the pair first, because intra pair skew converts to common mode noise. Then match between pairs if the receivers must stay in phase with each other.
Can the termination resistor be shared between two receivers? No. A shared resistor terminates only the common node, and each branch sees an unmatched line. Terminate each input at its own pin.
How much copper is needed under a clock buffer? Enough to spread the dissipation into the plane, typically a few square millimetres connected by several vias. The package thermal resistance sets the requirement, not the copper area alone.
