Additive PCB Manufacturing: SAP and mSAP for Fine Lines
Why Additive Processes Exist
Conventional board fabrication is subtractive. It begins with copper already covering the laminate and removes everything that is not part of the circuit, which means the process is limited by how precisely the etchant can be told where to stop. As the copper thins during etching, the etchant also attacks the sides of the trace, so a trace designed at 40 microns finishes narrower and with a trapezoidal cross-section.
That behaviour sets a practical floor on line width and creates a second problem: the thinner the copper, the less current the trace can carry and the more its resistance matters. Additive processes avoid the trade-off by building the conductor up where it is needed instead of cutting it down, which is what makes line widths of 30 microns, 20 microns, and below manufacturable in volume.
Subtractive and Additive Compared
In a subtractive flow, the copper is uniform before imaging and patterned by etching. Waste is inherent, because the removed copper is not recovered in any usable form, and the etchant load grows with copper thickness. Line width, spacing, and copper thickness are coupled: increasing copper thickness to carry more current also widens the undercut.
In an additive flow, a thin conductive seed or catalytic surface is created and copper is deposited only in the areas that will become conductors. Copper thickness is built after the pattern is defined, so a 20 micron line can carry useful current without the geometric penalty. Material use is lower and the chemical load of the etch step falls, which is a real cost and environmental advantage at volume.
The Three Additive Routes
Full additive processing deposits the entire conductor by electroless copper on a catalysed substrate with no seed etch. It offers the best copper utilisation and the finest features, but the chemistry is demanding and the process window is narrow, so it is used in specialised work rather than mainstream board production.
Semi-additive processing, usually written SAP, is the workhorse of high-density interconnect. A very thin copper seed layer is sputtered or electroless-plated onto the substrate, photoresist is imaged over it, copper is electroplated into the openings to build the traces, the resist is stripped, and a short flash etch removes the seed between conductors. Line widths of roughly 15 to 30 microns are routine, which covers the routing density of modern HDI boards.
Modified semi-additive processing, mSAP, tightens the same sequence with thinner seed layers, finer resists, and tighter process control. It reaches line widths below 10 microns and is the technology behind substrate-like PCBs and advanced packages, including the fine-line layers used under high pin-count devices.
Process Flow Step by Step
The flow starts with substrate preparation. Surfaces are cleaned and chemically treated so that the copper that follows adheres reliably, which matters more here than on a conventional board because the deposited layer is thin.
Next comes the seed. Sputtering produces a very thin, uniform conductive layer on rigid substrates, while electroless deposition is used where the surface geometry is more complex. The seed is not the conductor; it is the electrode that makes electroplating possible.
Photoresist is then laminated, exposed, and developed to open the areas that will become traces. Copper is electroplated into those openings until the target thickness is reached, typically around 20 to 25 microns for the finished conductor. The resist is stripped away, and the thin seed between traces is removed with a controlled flash etch that is short enough not to measurably attack the plated traces.
From there the panel follows the familiar path: solder mask, surface finish such as ENIG or OSP, electrical test, and final inspection. The extra care is concentrated in the imaging and plating steps, not in the back end.
What Fine Lines Change
Thinner traces let a designer place more routing channels between the pads of a fine-pitch package, which is what allows a high pin-count device to escape on a smaller number of layers. That reduction in layer count partly offsets the higher cost per layer, and it also shortens the vertical transitions that degrade a fast signal.
Better geometry helps signal integrity directly. A rectangular conductor with controlled cross-section behaves more predictably than an etched trapezoid, and the ability to pair fine lines with thin dielectrics makes it easier to hold a target impedance across a dense routing area. Power delivery improves as well, because the same area can hold more copper when the traces are narrower and the spacing tighter.
Materials and Substrates
Rigid FR-4 remains the common choice for SAP layers, with high-Tg and low-loss grades selected when the board also carries high-speed signals. Polyimide is used for flexible and rigid-flex constructions, and ceramic or specialised carriers appear in package substrates.
Dielectric thickness matters as much as line width in these designs. Thin prepreg and fine lines go together, because the impedance of a 20 micron trace can only be held if the dielectric height is controlled just as tightly. This is why additive processes and advanced lamination capability usually arrive together in a fabricator’s roadmap.
Limits and Engineering Challenges
Adhesion is the first risk. A thin seed layer on a smooth substrate is easy to damage during handling, and any contamination before plating shows up as a lifted trace. Cleanliness and controlled storage between steps are not optional.
The flash etch is the second risk. It must remove the seed completely without eating into the plated conductor, and the margin between those outcomes narrows as lines get finer. Uniform electroplating across a large panel is the third challenge: current density varies with pattern density, so a dense area and a sparse area on the same panel can end up with different copper thickness unless the plating is actively balanced.
Yield and inspection follow. Fine lines are harder to inspect optically and easier to damage, so handling systems and inspection recipes have to be matched to the feature size rather than inherited from a conventional line.
Where Additive Boards Are Used
The obvious applications are those that need density: smartphone and wearable main boards, high-density interconnect in servers and networking equipment, antenna-in-package modules in 5G and mmWave radios, and package substrates for processors and AI accelerators. Automotive electronics are another growing area, where fine-line HDI supports radar modules and dense control hardware in space that is tight and thermally stressed.
Medical devices and miniature sensors use the same capability when the product must fit a physical envelope that a conventional board cannot meet.
Working With a Fabricator
Ask for the line width and spacing the process actually guarantees in production, not the best number achieved in a laboratory, and ask how that capability is verified. A good discussion covers the dielectric thickness the fine lines will sit on, the impedance targets, the plating thickness tolerance, and how coupons will be used to confirm the result.
Because fine-line capability only pays off when the rest of the board matches, it is worth confirming that lamination, drilling for microvias, and surface finish are all in the same facility. Splitting a fine-line core across two suppliers usually costs more in yield than it saves in price, and a partner experienced in PCB manufacturing and PCB capabilities can flag the design rules that matter before the panel is tooled.
FAQ
What line width can additive processes reach? SAP is typically used from about 15 to 30 microns, and mSAP reaches below 10 microns. Conventional subtractive etching becomes difficult below roughly 50 microns.
Is additive manufacturing more expensive? Per layer, yes, because the imaging and plating are tighter. The benefit comes from needing fewer layers and smaller boards, which can bring the finished assembly cost down.
Does additive copper behave differently? The copper is electroplated in both processes, so the grain structure is comparable. The difference is the geometry: a rectangular cross-section instead of an etched trapezoid.
Can additive boards carry power? Yes. Thickness is built after imaging, so a fine trace can be plated thicker without the width penalty that subtractive etching imposes.
Do I need a special surface finish? No. Standard finishes such as ENIG and OSP are applied at the end of the same flow, and the choice is driven by the assembly process, not by the additive step.
Conclusion
Additive processing exists because etching has a floor, and modern products keep asking for routing density below that floor. SAP and mSAP build the conductor where it is needed, which delivers fine lines, better impedance behaviour, and less wasted copper. The trade-off is a tighter process that demands control over adhesion, plating uniformity, and seed removal. For designers, the practical question is not which process is more modern but which one matches the line width and density the product needs. For the surrounding steps, see our notes on PCB design and layout and quality management.
