PCB Eye Diagrams: Reading Signal Quality at Speed

One Picture That Summarises the Whole Channel

An eye diagram compresses everything that happens to a high speed signal into a single image. Thousands of individual bit periods are overlaid on top of each other, synchronised to the clock, and what emerges is a shape that shows how much margin the link has. A wide open pattern means the receiver can tell a one from a zero with room to spare. A closing pattern means the receiver is working with a shrinking window, and the bit error rate will eventually pay for it.

For a board designer the eye diagram is useful because it points back to physical causes. Every reflection, every impedance change, every unwanted coupling path in the layout leaves a mark on that shape, and reading those marks is how a layout problem becomes fixable.

What the Diagram Shows

Three measurements describe an eye. The eye height is the vertical opening between the one and zero levels, which is the voltage margin available to the receiver. The eye width is the horizontal opening, which is the timing margin. The crossing percentage and the shape of the transitions describe how symmetrically the signal rises and falls. Where an eye is measured against a mask, the mask defines the region the signal must not enter, and the margin is the distance between the trace and the mask edge.

Jitter appears as thickness in the transitions rather than as a single clean edge, because the crossings move from bit to bit. Rise time and fall time set the slope of the transition and therefore how much of the unit interval is consumed by switching rather than by settled levels. Together these quantities define a bit error rate, and the bit error rate is the number the system actually has to live with.

What Closes the Eye

Several mechanisms narrow the opening, and they tend to arrive together.

• Reflections. When a signal meets an impedance change, part of its energy returns to the source and part continues. The returning energy arrives later, adds to or subtracts from the signal, and produces ringing, overshoot and error. This is the mechanism that a controlled impedance stack-up exists to prevent.
• Ringing and overshoot. Inductance in the path and discontinuity in the geometry cause the signal to overshoot and then oscillate around its final level, eating into both voltage and timing margin.
• Jitter. Reflections and coupling shift the position of the transition from bit to bit, which is jitter, and jitter directly reduces the eye width.
• Crosstalk. Energy coupling from neighbouring traces adds noise that the victim did not send, which raises the noise floor and closes the eye from above and below.
• Loss. Conductor loss through the skin effect and dielectric loss both attenuate the high frequency content of the signal, which slows the edges and closes the eye over distance. This is the mechanism that limits how far a signal can travel on a given material.
• Inter-symbol interference. The accumulated effect of loss and reflections from previous bits arriving at the wrong time, which is worse at higher data rates.

The Board Features Behind Them

Each of those mechanisms traces back to something in the layout or the fabrication. Trace width and copper thickness vary with the etching process, and a small width change alters the impedance. The dielectric constant of the laminate varies between batches and even across a panel, because resin content and glass weave are not perfectly uniform, and the dielectric thickness varies with the lamination process. The stack-up itself introduces layer transitions, and every via is a discontinuity: the stub left by an unused via barrel, an oversized pad, and an anti-pad that is too small all disturb the impedance.

Manufacturing tolerance ties these together. Etch precision, plating thickness, lamination pressure and drilling accuracy all move the geometry that the design assumed, which is why the specification discipline described in our PCB manufacturing notes and the verification covered in our notes on TDR impedance testing matter as much as the schematic.

Jitter, and Why It Is Not Just a Clock Problem

Jitter has a random component, which is unavoidable and grows with noise, and a deterministic component, which is caused by the system and can therefore be reduced. Reflections are the most common deterministic source on a board. Because the reflected energy depends on the bit pattern that preceded it, the resulting timing shift is data dependent, which is why it is sometimes described as pattern dependent jitter. Duty cycle distortion, crosstalk from switching neighbours and noise on the reference plane all add to the deterministic total.

The practical consequence is that a link can pass a functional test and still fail in the field, because jitter reduces the timing window until the bit error rate exceeds what the protocol tolerates. Reducing the reflections is the same work as widening the eye, which is why the two problems are usually solved together.

Return Paths and Crosstalk

A signal is only half of a circuit. The current returns through the reference plane directly beneath or above the trace, and the area of the loop it encloses determines both the impedance and the radiation. Anything that obstructs the return path, such as a split or a gap in the plane, forces the return current to divert, which raises the impedance locally, increases the loop area and couples energy into neighbouring traces.

Two rules follow, and they are the ones that most often distinguish a working high speed layout from one that is merely tidy. Keep a solid, continuous reference plane under every fast signal layer. And keep the loop small by routing the signal close to its reference and by not routing fast nets across plane boundaries. The result is lower crosstalk, lower emissions and a more stable impedance, and it is part of the same layout discipline described in our PCB design and layout notes.

Simulating Before the Layout Is Released

Signal integrity simulation has to happen before the board is fabricated, because that is the only point at which the layout can be changed cheaply. A field solver that models the real stack and the real geometry will predict the impedance of each structure, the loss along the channel and the resulting eye at the receiver. Running that on the worst case net, and on the via transitions that the worst case net uses, catches most of the problems while they are still editable.

The simulation is only as good as the stack data it is given, and a stack that has not been confirmed with the fabricator is an assumption. High density designs, where fine features and many layer transitions make the analysis harder, benefit most from running the simulation early, which is one reason HDI PCB projects place so much emphasis on stack-up agreement before routing begins.

Measured After Build

Once the board exists, three measurements close the loop. TDR on a coupon confirms the impedance along the trace and reveals the discontinuities in it. A vector network analyser measures insertion loss and return loss across frequency, which is the metric that determines how much of the signal survives the channel. And eye measurement on the assembled board, or a bit error rate test, shows what the receiver actually sees in the finished product, including the effects of the package, the connector and the enclosure.

The board level work that keeps the eye open is largely a list of discipline rather than of cleverness:

• Hold the trace geometry constant, including the width and the spacing, as the trace travels.
• Minimise layer transitions on fast nets, and remove via stubs with back drilling where a transition is unavoidable.
• Use blind and buried vias where they can shorten the stub.
• Size the anti-pad and the via pad for the impedance requirement rather than for the drill programme.
• Keep the reference plane continuous, and never route a fast signal across a split.
• Space aggressor and victim traces according to the coupling the design can tolerate, and consider shielding or ground stitching between sensitive groups.
• Match lengths within differential pairs and within parallel buses, because skew between two halves of a pair converts differential signal into common mode noise.

Materials and Cost

Dielectric loss falls as the loss tangent falls, so a low loss laminate widens the eye on a long channel. A more stable dielectric constant also makes the impedance easier to hold, which reduces reflection. Both come at a price, and the sensible engineering decision is to identify which nets actually need the better material rather than specifying it for the whole board. Our overview of PCB capabilities sets out what is available and what each option costs, and in most cases the largest gains come from fixing the layout rather than from changing the laminate.

Frequently Asked Questions

What is a good eye opening? It depends on the interface and its mask. The useful measure is the margin between the measured eye and the mask the standard specifies, not an absolute size.

Can a board pass functional test and still have a closed eye? Yes. A link can work at low error rates and fail later as temperature, voltage and data patterns vary. The eye and the bit error rate are the honest measures.

Which layout change helps most? Usually removing the largest reflection, which is often an unnecessary layer transition or a via with a long stub, followed by fixing a broken reference plane path.

Does a low loss laminate always help? It helps on long, loss dominated channels. On a short channel dominated by reflections, fixing the layout is far more effective.

When should simulation be run? Before the layout is released, on the worst case nets and their via transitions, using a stack that has been confirmed with the fabricator.

Conclusion

The eye diagram is the summary of the channel, and every feature in it has a physical cause in the board. Reflections from impedance changes, ringing from discontinuities, jitter from pattern dependent reflections, crosstalk from coupling and loss from the material all write themselves into the shape, and each can be traced back to a layout decision or a manufacturing tolerance. Simulate the channel before releasing the layout, verify the impedance on the finished panel, and keep the reference plane continuous and the geometry constant. Do that, and the eye stays open by design rather than by luck.