PCB Jitter: Sources, Measurement and Layout Fixes

Jitter is the reason a link that works perfectly at room temperature on the bench fails at temperature in the field, and the board is usually blamed last even though it is often responsible. This article explains what jitter is, which parts of it the PCB contributes, how it is measured, and which layout decisions actually reduce it.

What Jitter Is

Jitter is the variation in the arrival time of a signal edge compared with where it should have been. A transmitter that is perfectly locked still produces edges that move a little from one bit to the next, and everything the signal passes through on the way to the receiver adds more variation.

It is normally split into two components because they behave differently. Random jitter comes from noise, follows a Gaussian distribution, and has no bounded peak, so it is described by its root mean square value and it keeps growing as more bits are measured. Deterministic jitter is bounded, repeatable and comes from a specific mechanism such as a reflection, a duty cycle error or a pattern dependent effect, so it can in principle be measured and subtracted.

Total jitter is the sum of the two, and the way they combine matters at low bit error rates. Deterministic jitter adds directly, while random jitter has to be multiplied by a factor that depends on the target bit error rate, so a link specified at 1e-12 is far more sensitive to random jitter than one specified at 1e-9. This is why a design can pass a bench test with an eye diagram that looks comfortably open and still fail in production, where the required confidence is much higher.

Why the Board Matters

The PCB is a passive channel, so it cannot create jitter out of nothing. What it does is take the jitter that already exists and multiply it, by spreading edges in time and by letting noise modulate the point at which the receiver decides.

The mechanism is easiest to see with an eye diagram. A clean transmitter produces an eye with fast, consistent crossovers. Send the same signal down a lossy, mismatched trace and the eye closes from both sides: the vertical opening shrinks because the levels sag and smear, and the horizontal opening shrinks because slow edges sit differently depending on the data pattern. The horizontal shrinkage is jitter, and it appears even though nothing on the board is actively adding noise.

There is a second path that is more subtle. Any noise on the ground or power plane changes the switching threshold of the receiver, which moves the point in time at which the input is sampled. That is why a board with a noisy plane can show more measured jitter than the same layout with a solid, well decoupled reference, even though the traces themselves are identical.

The Sources the Board Controls

Five mechanisms account for most of the jitter a layout can influence.

Loss and pattern dependent timing. A lossy trace attenuates high frequency content more than low frequency content, so a slow edge arrives later than a fast one and the timing of an edge depends on the bits that came before it. The effect is called intersymbol interference, and it is the dominant jitter mechanism on long channels at multi gigabit rates. It worsens with trace length, with higher dielectric loss and with skin effect on narrow traces.

Reflections. Any impedance discontinuity sends part of the signal back. A via stub, an uncontrolled connector, a branch, or a trace whose width changes abruptly all produce reflections that arrive after the main edge and disturb the next one. On a differential pair a mismatch between the two halves turns part of the signal into a common mode component, which radiates and which the receiver rejects imperfectly.

Crosstalk. A nearby aggressor couples into the victim and adds a delayed, data dependent disturbance. Because the coupling depends on the aggressor pattern, the resulting jitter is deterministic, and it often shows up as two or more discrete peaks in a jitter histogram rather than a smooth distribution.

Duty cycle distortion. If the rise and fall times of a differential pair differ, or if the positive and negative halves are not symmetric in length, the crossing point of the pair drifts and the eye closes asymmetrically. Asymmetric termination or an unbalanced reference voltage can do the same thing.

Power and reference noise. Simultaneous switching of many outputs pushes current through the plane and package inductance, moving the local ground reference. A receiver whose threshold moves samples at the wrong instant, and the resulting jitter is correlated with the activity of the rest of the device.

Measuring It

Jitter is measured either in the time domain, by recording the deviation of each edge from its ideal position, or by building up an eye diagram and reading the statistics from it.

The time domain method produces a time interval error record, which is simply the difference between when an edge arrived and where it should have been, plotted against the bit sequence. Statistical processing of that record separates the random and deterministic parts and produces a bathtub curve: the bit error rate plotted against the sampling instant, which is the practical way to predict whether a link will meet a target error rate with margin. An eye diagram measured on a scope is the same information presented as an image, and its width at the decision threshold is the total jitter for the population measured.

For the board specifically, two measurements are worth separating from the rest. One is the impedance profile along the channel, which is what a TDR measurement provides; it identifies the discontinuities that will generate reflections, in the order they appear. The other is intra pair skew, which is the difference in propagation delay between the two halves of a differential pair and which a time domain measurement on a test coupon can resolve directly. Both are board properties rather than device properties, and both can be improved without changing the silicon.

Layout Practices That Reduce Jitter

• Keep the channel impedance controlled from driver to receiver, and keep the transmission line reference plane solid under the whole route. A plane split under a trace is worse than a longer trace.
• Remove via stubs. On a thick backplane a stub of a few millimetres is enough to create a visible reflection, which is why back drilling exists. On thinner boards keep the transition to a layer adjacent to the reference and use a ground return via next to every signal via.
• Space differential pairs from aggressors, and keep the intra pair spacing constant along the route. Changing spacing to squeeze past an obstacle changes the differential impedance and creates the discontinuity the pair was routed carefully to avoid.
• Match the two halves of a pair in length, and correct any mismatch close to where it occurs rather than at the end of the route. A pair that is matched in total length but mismatched over a section still produces skew.
• Keep trace length to the minimum the layout allows. Loss, and therefore intersymbol interference, grows roughly with length, so a shorter route is almost always a lower jitter route.
• Provide a low impedance return path. Decoupling close to the device, thin dielectric between power and ground, and a continuous ground plane all reduce the reference noise that converts into timing error.
• Control the layer transitions. Each change of layer is a change of reference, and an unplanned one introduces both a reflection and a return path break.

Length matching between parallel buses deserves a note because it is often applied too eagerly. Matching a clock to a data bus, or two halves of a differential pair, is useful. Matching unrelated nets that toggle at different times often wastes routing area and adds length, which increases loss. Skew matters most where it is compared directly, which is why trace skew is treated as a separate budget item from loss.

Materials and Stackup

The dielectric determines how much of the signal survives the journey, and therefore how much pattern dependent jitter the channel contributes. Standard FR-4 works well up to a few gigabits per second over short routes, but its loss rises sharply with frequency, and at 10 Gb/s and above the eye closing from a long FR-4 channel becomes the limiting factor.

Lower loss materials, thinner dielectrics and a wider trace all reduce attenuation. A wider trace lowers the resistive component, a thinner dielectric raises the capacitance and allows a narrower trace for the same impedance, and a lower dissipation factor material reduces the dielectric loss. The trade is cost and, in some cases, manufacturability, since very low loss laminates behave differently in drilling and lamination. Choosing that stackup early, together with the fabricator, is the cheapest way to keep jitter under control, because changing the material after the design is complete means changing the whole design.

FAQ

• Can a PCB add random jitter? Not directly, because random jitter comes from noise. The board amplifies it by attenuating the signal, which reduces the slope at the crossing and turns a given amount of noise into more timing error.
• How much jitter is acceptable? It depends on the standard. The budget is defined by the protocol, and the board contribution is whatever is left after the transmitter and receiver are accounted for.
• Does a longer trace always increase jitter? Yes, for a lossy channel. The effect is stronger at higher data rates and with higher loss materials.
• Is jitter the same as skew? No. Skew is a static time difference between two signals. Jitter is variation over time on a single signal or link.

Summary

Jitter is a system property that the board can make worse in five ways: loss that spreads edges depending on the data pattern, reflections from impedance discontinuities, crosstalk from neighbouring routes, duty cycle error from asymmetric pairs, and reference noise that moves the receiver threshold. None of these can be removed by a single layout trick, but all of them respond to the same habits: a controlled impedance channel with a solid return, short routes, no stubs, clean layer transitions and enough spacing around fast nets.

The measurements that matter are the eye or the time interval error record, the impedance profile and the intra pair skew, and all three are board properties that can be improved before the design is released. Where the channel is long or the data rate is high, the stackup and material choice belong in the same conversation, which is why high frequency boards are best planned with the fabricator during the layout stage rather than after the first prototype fails to meet its error rate target.