24 Tips for Noise Reduction and EMI Control in PCB Design

Noise control on a board is not a single technique; it is a collection of small decisions that each remove one path for energy to travel. Every one of them closes a route by which electromagnetic interference leaves the board or enters it. Taken one at a time, several of them look like a preference. Taken together, they decide whether a product has margin or whether every test is a fight. The list below is the working set: twenty four items, grouped by the stage of the design at which each one is decided.

Component Selection

1. Use the slowest logic family that meets the timing requirement, and reserve the fast devices for the places where they are needed. A slower edge has less high-frequency energy by definition.
2. Where a signal does not need its natural edge rate, add a series resistor at the driver to slow the transition. This is one of the cheapest noise reduction measures available, and it costs one part.
3. Give inductive loads some form of damping. A relay coil or a solenoid that switches without a suppression path generates a large transient that will find every nearby trace.
4. Choose the lowest clock frequency the system can accept. Every reduction of the clock frequency lowers the frequency of the harmonics that have to be managed.

Placement

5. Place the clock generator close to the device that consumes the clock, and ground the crystal package. A long clock trace is a radiating element and a receiver.
6. Surround the clock area with a ground structure and keep the clock traces as short as the layout allows.
7. Place the I/O driver circuits near the board edge so that the signal leaves the board quickly, and filter both the signals entering the board and the signals coming from a noisy area. Series termination reduces reflections at the same time.
8. Partition the board by frequency and by switching current. Keep the noisy components physically separated from the quiet ones rather than interleaved with them.
9. Keep clocks, buses and chip select signals away from the I/O lines and the connectors.
10. Keep analog input lines and reference pins away from digital signals, and especially away from clocks.
11. On a converter that has both domains, keep the digital section and the analog section clearly separated rather than interleaved, so the boundary can be managed.
12. Run the clock traces perpendicular to the I/O lines where they must be near each other, and keep the clock components away from the I/O cables. Parallel routing couples far more than crossing.

Terminations and Unused Pins

13. Never leave an unused logic input floating. Tie it high, tie it low, or define it as an output with a defined state.
14. Connect every supply and ground pin on an integrated circuit. A supply pin that is left unconnected on the assumption that it is internally bonded is a part that behaves unpredictably.
15. Terminate an unused operational amplifier properly: its non-inverting input to ground and its inverting input to the output. An unterminated amplifier is an oscillator.

Routing

16. Use 45 degree corners rather than 90 degree corners. A right angle is a discontinuity that increases both emission and coupling.
17. Keep component leads and, above all, decoupling capacitor connections short. A capacitor with a long lead has an inductance that cancels its purpose at the frequency where it is needed.
18. Make critical traces wide, and guard the noise-sensitive ones with ground on both sides. High-speed traces should be short and straight rather than routed for convenience.
19. Do not run noise-sensitive lines parallel to high-current or fast switching lines, and do not share a return with them.
20. Do not route under a crystal or under any device that is sensitive to what is routed beneath it.
21. Avoid forming a current loop around low-level or low-frequency circuits. Small signals in a loop are efficient receivers.
22. Avoid loops in signal paths generally. Where a loop cannot be avoided, make it as small as the layout permits, because the loop is the antenna.

Ground, Power and Capacitors

23. Place one decoupling capacitor beside each integrated circuit, and add a small high-frequency bypass capacitor beside every bulk electrolytic capacitor. The bulk part handles the low-frequency transient and the small part handles the edge.
24. For circuits that store and release energy, prefer a large tantalum or film capacitor to an electrolytic, and ground the case of a tubular capacitor. Electrolytics are poor at the frequencies a switching circuit produces.

Two further rules apply to the ground and power structure and are worth stating separately, because they govern everything above. On a two-layer board, use a single point connection for the supply and for the ground, and keep both conductors as wide as the layout allows. If the budget permits a multilayer construction, take it, because a ground plane and its companion power plane reduce the inductance of the supply and the ground more than any arrangement of traces can.

Using the List

The items are not equally important, and applying all of them to every net is neither possible nor necessary. The ones with the largest effect are the ones that reduce loop area: the ground and power structure, the placement of the decoupling capacitors, the separation of noisy and quiet circuits, and the routing of the fastest nets. The items that slow edges and remove discontinuities come next. The remaining items are refinements that matter at the margin.

A board that follows the first group will usually pass with margin, and a board that ignores it cannot be saved by the refinements. This is the reason a review that starts with the ground structure finds more problems than a review that starts with the trace geometry, and it is the order our design review follows.

The same list is also a manufacturing list, because several of the items change what the fabricator has to hold: wider critical traces relax the etching tolerance, ground fill changes the copper balance, and the decoupling population changes the assembly data. Reviewing the two together is what keeps a quiet design buildable, which is why the same data set goes to our PCB manufacturing and SMT assembly reviews.

One further practice is worth adding. Write down which nets received which treatment, and why. A note that three interfaces carry series terminators, that the clock section is enclosed by ground and that the analog input to the converter is referenced to its own ground gives the next engineer a starting point and gives the next review a checklist. Without it, a later revision that removes a resistor to improve a rise time has no way of knowing what the resistor was protecting, and the problem it was solving returns. The note travels usefully as well: an assembly partner who knows that a particular pad pattern is deliberate will query a change rather than build it.

FAQ

Which single tip has the largest effect? Reducing the area of the current loops, which in practice means giving every fast net a continuous return path close to it.

Is a series resistor always a good idea? No. It slows the edge, which reduces emission, but it also changes the timing and the drive strength. It belongs on lines that do not need the bandwidth.

Do these rules apply to low-speed boards? Most of them do, because the edge rate rather than the clock frequency determines the behaviour. The ground and return path items apply to every board.