DDR4 SDRAM Design Points and Their Layout Consequences

Fourth generation memory changed the layout problem rather than only the data rate. The supply fell to 1.2 V, the bus moved to a point-to-point arrangement with on-die termination, and a set of training routines moved into the controller to absorb the timing that the layout used to have to guarantee. Understanding which of those changes the layout still controls, and which it no longer does, is the difference between a board that trains and a board that will not boot at speed.

What DDR4 Changed

The headline is the transfer rate, but the changes that affect a layout are specific. The interface runs from a lower supply, so the noise margin per bit is smaller and the reference has to be cleaner. The data bus is point to point between the controller and one device rather than a shared bus, which removes the tree structure that earlier generations used. On-die termination is built into the devices so that external terminating resistors are reduced or removed on the data lanes. The DDR4 SDRAM command and address bus is still shared between devices, and it is now routed as a daisy chain rather than as a tree.

The other half of the change is in the controller. Write leveling, read gate training, reference voltage training and command bus training are routines that the controller runs at start-up to measure the delay to each device and compensate for it. Those routines absorb a large part of the skew that a layout cannot control, which relaxes some rules and makes others more important.

<img src="https://www.gopcba.com/wp-content/uploads/2026/05/体外除颤仪PCBA.png" alt="DDR4 memory devices routed in fly-by topology” />

Fly-By Topology and Why It Replaced the Tree

The fly-by topology routes the command and address bus from the controller past each memory device in turn, with a short stub to each one. The trace therefore has a different length to every device, and the signal arrives at each of them at a slightly different time. In a tree, the branches were matched so that every device saw the signal simultaneously, which is why earlier layouts spent so much effort on equal-length routing.

Fly-by is used because it produces a clean transmission line along the bus with small stubs, and because the timing difference it creates is exactly what the training routines measure. Two rules matter with it. The stub to each device must be as short as the layout allows, and the trace should enter each device pad at an angle rather than at a right angle, so that the discontinuity at the pad is minimised. The bus should stay on one layer, with no vias, for the same reason.

The ordering of the devices along the bus is also a decision. The load on the bus is the same whichever order is used, but the physical arrangement determines the stub lengths, and the layout that keeps every stub short and every device close to the line is the one that trains most easily.

Termination and ODT

The data lanes are point to point and terminated inside the device. The on-die termination value is selected by the controller, and it changes during operation: the device that is writing terminates its receiver, and the device that is reading drives while the other end terminates. The layout has no control over the setting, but it does control whether the line is a clean transmission line between the two ends.

The command and address bus is terminated at the far end, either with a resistor network or with the die termination of the last device, depending on the design. The termination has to be placed at the physical end of the bus rather than at a convenient point, because a trace that continues past the termination is a stub that reflects.

<img src="https://www.gopcba.com/wp-content/uploads/2026/06/EV-System-Integration.jpg" alt="byte lane routing with matched data and strobe” />

Training, and What the Layout Owes It

Write leveling adjusts the timing of the write data so that it arrives at the device coincident with the clock. It works by having the device sample the clock with the data strobe and report the phase back to the controller, which then delays its output per byte lane. The routine needs the clock and the strobe to be routed on similar paths, and it needs the skew within a byte lane to be small enough that a single delay value works for all the bits.

The read path uses gate training, which positions a sampling window on the incoming strobe. Command bus training adjusts the address and command timing per device. Reference voltage training uses the internal reference to find the centre of the input eye.

The consequence for the layout is a budget that is easier to state than to check. Within a byte lane, the data bits and the strobe have to be matched closely, because no training can correct a difference between bits that share a strobe. Between byte lanes, the skew is absorbed by per-lane training, so the matching requirement is much looser. On the command bus, skew between devices is absorbed by training, so the rule that matters is the stub length rather than the total length.

Layer and Reference Rules

Every memory signal should be routed over a continuous reference plane, and that reference should not change along the route. Where the bus must change layers, the return path has to be stitched beside the signal via, and the number of such transitions should be kept to a minimum.

The data lanes benefit from being routed on the same layer as the strobe, on adjacent layers within a stack-up that puts them against the same plane, or on layers that mirror each other in the stack. Where two byte lanes share a routing channel, they should be separated by enough spacing that the crosstalk between them stays inside the budget.

The supply is a layout item in its own right. The memory rail supplies a fast switching load, so the decoupling population belongs beside each device rather than at one point on the rail, and the plane pair under the devices should be as thin as the stack allows. The additional supply required by the memory devices has its own decoupling requirements and its own trace width. Our design and layout team treats the memory interface as a review item on its own, and the stack-ups that make a thin plane pair possible are listed on our PCB capabilities page.

Verification Before Release

The checks that catch most problems are geometric and can be run as a report. Compare the length of every data bit and its strobe within a byte lane. Confirm that no memory trace changes reference plane without a return via. Confirm that every stub is inside the length budget and that no trace extends past its termination. Confirm that the spacing between byte lanes is as intended.

Those checks do not prove the interface will work at its rated speed, which requires a signal integrity simulation of the channel including the package models and the device models, but they do find the layout mistakes that no amount of training can compensate for. Where the design will be built in quantity, the same interface is worth building once as a prototype so the training margin can be measured rather than assumed; our rapid PCBA prototyping service is used for exactly that.

FAQ

Do DDR4 data lines still need length matching? Within a byte lane, yes, and closely. Between byte lanes the skew is absorbed by per-lane training.

Can the command bus change layers? It can, but every layer change adds a discontinuity that the training has to absorb, and a bus routed on one layer with short stubs is easier to bring up.

Why is the stub length so important? A stub is a transmission line that reflects energy back into the bus, and its effect grows with the data rate. Short stubs keep the bus a clean line.