EMC Design From the Layout Stage

Many products discover that they do not pass electromagnetic compatibility testing late in development, and the correction takes several rounds, costs money and moves the launch date. The root of the problem is usually already present in the board, because a shield added over a radiating loop and an absorbing material stuck to a case treat the symptom rather than the source. EMC design means taking the decisions in the schematic, the stack-up and the layout, where they are still cheap.

What the Service Covers

The work is not a final inspection. It starts with the choice of components and runs to the released artwork. The schematic is reviewed at the blocks that matter for compatibility: the supply filtering, the protection on the interfaces, the clock circuit and the reset circuit. The stack-up and the reference planes are planned, and the controlled impedance is calculated, because a stack-up that provides a continuous reference is the foundation everything else stands on.

The layout then follows a plan. The digital, the analog and the power sections are separated, a source of interference is kept away from a circuit that is sensitive to it, and the input and output connectors are grouped so that they can be filtered together. The critical routing, including the high speed signals, the clock lines and the supply return paths, is arranged so that the area of the loops is small, because the area of a loop is what radiates.

Five Points That Decide the Result

The stack-up is the first. A board with four or more layers behaves very differently from a two layer board, and the working principle is that every signal layer has an adjacent reference plane. An edge rule is also applied, in which the power plane is pulled back from the edge of the ground plane so that the fringing field at the edge of the board is reduced.

Partitioning is the second. The switch mode supply, the power drivers and the clock circuits are placed towards the edge of the board, away from the analog inputs and the sensor interfaces. The interfaces are concentrated on one side so that filtering and grounding are handled once rather than in several places. A ground strip between partitions reduces the coupling between them.

Grounding is the third, and it accounts for most of the failures that are seen. A continuous reference plane is maintained, and it is not cut by a slot that forces a return current to take a long path. A high speed trace keeps a complete reference underneath it. Where an analog and a digital ground are separated, they are joined at a single point or through a bead rather than connected everywhere. A row of stitching vias around the edge of the board makes the edge behave like a screen. The seventh design point in many checklists is the simple one that matters more than the rest.

Filtering is the fourth. A common mode choke and differential capacitors sit at the supply inlet, and a decoupling capacitor is placed immediately beside each supply pin of an integrated circuit, with the high frequency and low frequency parts of the requirement both covered. An interface that carries a signal out of the board is given an RC filter, a transient suppressor or a common mode choke according to its rate. A filter only works if the component is placed where the interference is, so the position of the part is part of the design rather than a detail of the placement.

Shielding is the fifth, and it is used where the layout alone cannot reach the requirement. A radio frequency section or a fast clock can be given pads and grounded vias for a metal can, the points at which the board connects to the chassis are planned deliberately, and a connector on a critical signal can be given its own shield connection. Shielding works with the mechanical design rather than instead of it, and a can that is not connected properly makes the result worse rather than better.

<img src="https://www.gopcba.com/wp-content/uploads/2026/08/types-of-pcb-assembly-techniques.webp" alt="ground plane and stitching vias on a multilayer board” />

How the Work Is Sequenced

The application, the level of certification the product has to reach and the signalling rate are established first, and a strategy and a stack-up follow. The schematic is then reviewed at the blocks listed above and suggestions are made while the drawing can still be changed.

The measures are then implemented during the layout, and a dedicated review is held at the end against a check list, with a report of the findings and the changes recommended. For high speed boards, a signal integrity and power integrity simulation can be added so that the behaviour of the critical nets and the noise on the supply are predicted before the board is built rather than measured afterwards.

The comparison between a conventional approach and an optimised one is instructive. The conventional board places the blocks where they fit, uses one decoupling capacitor per device, routes the clock on an outer layer as a short trace, and spreads the interfaces around the outline. The optimised board plans for four or more layers with complete references, groups the blocks by the strength of the interference they produce, sizes the decoupling to the supply pins, routes the clock on an inner layer between ground, keeps the length matched, concentrates the interfaces on one side, and stitches the edge with vias. Almost none of those choices change the bill of materials, and together they change the measured result.

What Can Be Done to a Finished Design

A layout that has already been drawn can still be reviewed. The placement, the routing, the grounding and the filtering are examined and a list of findings and improvements is produced. If the board has not yet been fabricated, acting on that list is inexpensive and effective. If it has been built and has failed a test, the same analysis can be used to identify the cause of the excess and to propose a correction.

The cost of designing for compatibility is usually close to zero, because it is largely a matter of geometry and planning. In a minority of cases an additional filter component or a shield is needed, and the cost of that is small against the cost of a redesign after the certification test.

Our PCB design and layout group carries out the review and the layout work, and the resulting board goes into PCB manufacturing and then SMT assembly under the records held by quality management.

Where the Review Pays For Itself

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The savings are easiest to see on the products that carry a certification obligation and a fast interface at the same time: a design with a DDR memory, a high speed serial link, a switch mode supply or a radio. On those boards the difference between a layout that was planned and one that grew is usually the difference between one test round and three, and the cost of the extra rounds includes the board spins as well as the test house.

FAQ

Does designing for compatibility guarantee a pass? It raises the probability considerably, but the housing, the cables and the software also affect the result, so no supplier can guarantee the outcome of a certification test.

Can a completed layout be improved? Yes. The review produces findings and changes, and acting on them before fabrication is cheap and effective.

Does it increase the cost of the board? Rarely. Most of the measures are geometric. Where an extra filter or a shield is required, the cost is far below that of a post certification redesign.