Impedance Control Design Flow From Simulation to Layout

In a high speed digital or radio frequency design, the impedance along a trace is not a detail that can be left to the fabricator. The characteristic impedance of the transmission line has to be designed, and a mismatch produces reflections, ringing and bit errors that can stop a system working. The work therefore spans three stages: the calculation before the layout, the implementation during the layout, and the measurement after the board is produced.

When a Trace Has to Be Treated as a Transmission Line

The deciding question is the rise time. When the edge of a signal is faster than the delay along the trace, the trace behaves as a transmission line and its impedance has to be controlled. On a short board with a slow interface the effect is negligible, and on a fast interface it appears on a trace only a few centimetres long.

The applications that normally require it are the high speed digital links such as memory interfaces, serial buses, display links and Ethernet, the radio frequency paths between an antenna and a front end or a module in a fifty or seventy five ohm system, the differential pairs such as USB, low voltage differential signalling and Ethernet, and analog paths where the quality of the signal is the point of the product.

Stage One: Stack-Up and Calculation

Before any routing, the stack-up is designed from the layer count the customer requires, the material, and the target impedance values. The calculation uses a model matched to the structure: an outer layer trace over a plane is a microstrip, an inner layer trace between two planes is a stripline, a pair routed together is a differential structure, and a trace with ground either side on the same layer is a coplanar waveguide. Each has its own relationship between width, spacing and impedance.

The impedance control design covers single ended values from fifty to one hundred and twenty five ohms and differential values commonly between eighty five and one hundred ohms, with the ordinary tolerance at ten percent and seven percent achievable where the material and the process allow. Boards from two to thirty layers are covered, with FR4 for most work, a high frequency material where the loss matters and PTFE where the frequency is high enough to demand it, and a minimum trace width and spacing of three thousandths of an inch under standard conditions. Verification is planned at this stage as well, in the form of a test coupon measured by time domain reflectometry after fabrication.

Stage Two: Implementing It in the Layout

The calculated widths become constraints in the layout, and the critical signals are then routed to hold those constraints along their whole length. Four things decide whether the implementation survives the transition from the drawing to the board.

The reference plane has to be complete under the trace. A trace that crosses a split in the plane, or passes over a slot, sees a discontinuity in its return path and produces exactly the reflection the design was trying to avoid, even though the width was correct on the screen.

A signal that changes layer has to change its reference with it. A ground via beside the signal via gives the return current a short path, and the size of the anti-pad around the via is used to keep the impedance of the transition close to the impedance of the trace. A layer change with no return path is a discontinuity that no amount of width control will fix.

The width itself has to stay constant. A trace that narrows to pass between two pads, or that enters a pad much wider than the trace, creates a local change in impedance, and the correction is to keep the neck as short as the routing allows and to add a taper into the pad. Where the design requires it, a small series or shunt component is placed with the same care, because the pad it sits on is part of the path.

For a differential pair, the spacing and the length matter as well as the width. Holding the spacing constant keeps the differential impedance constant, and holding the length difference small keeps the two halves in phase. A pair that is split apart around an obstacle and rejoined has a discontinuity in the middle that shows up as a disturbance in the measurement.

<img src="https://www.gopcba.com/wp-content/uploads/2026/08/PCB-Assembly.jpg" alt="differential pair routing on an inner layer” />

Stage Three: Proving It on the Board

When the board is fabricated, coupons are placed at the edge of the panel and measured. The coupon is produced on the same panel, through the same lamination, etching and plating, and its structures are built on the same layers with the same widths and references as the controlled traces, which is what makes the measurement representative.

The instrument sends a fast edge along the line and reads the reflection, which gives the impedance at each point. That is more useful than a single number, because a uniform deviation points at the material or the process while an abrupt one points at a specific feature on the trace.

A simulation of the critical nets before the board is built complements the measurement. It shows whether the routing that was drawn will behave as intended while the layout can still be changed, which is considerably cheaper than discovering it from a working board that does not work.

What to Send

The work starts from the target impedance values, the signal types and rates, the layer count required, any preference in material, and the schematic or the interface description. From those, the stack-up and the width table are produced and issued for confirmation before the routing begins.

A two layer board can be controlled as well, using an outer layer microstrip, though the thickness and the width have to be chosen together and a very thin board may not allow a wide enough trace. Our PCB design and layout group carries the stack-up planning and the routing, PCB manufacturing produces the boards and the coupons, and the results are retained under quality management.

Where the Cost Sits

`r`n

Most of the benefit comes from the first stage, because a stack-up and a width table that were calculated properly remove the rework that otherwise appears after the board has been built. The layout stage consumes the most engineering time on a dense board, since constraining and checking every critical net takes longer than routing it once. The measurement stage is the smallest part of the cost and the one that produces the evidence a certification or a customer audit will ask for.

`r`n

It follows that the cheapest place to change a decision is before the routing starts. A stack-up that is revised after the layout is finished means the widths change, which means the critical nets are routed again, which is why the calculation is issued for confirmation rather than assumed.

FAQ

How is the work charged? From the layer count, the number of controlled structures, the signal rate and the complexity of the design, quoted after the board data have been reviewed.

Can a two layer board be controlled? Yes, with an outer microstrip structure, provided the board thickness and the trace width are chosen together.

What tolerance is realistic? Ten percent is normal on standard FR4, and seven percent is achievable where a tighter material tolerance and a controlled process are used.