BGA Fan-Out Design at 0.4mm Pitch

Ball grid array packages have become the standard for high performance devices, from processors and programmable logic to memory, because they allow the pin count to grow without the package growing with it. Designing a board for one is harder than designing for a leaded package, because the escape of the signals from under the device, the size of the vias, the pad geometry and the impedance all have to be planned together. The single most important decision is the fan-out strategy, and it follows from the pitch, the layer count and the signal rate rather than from a rule of thumb.

Pitch Determines the Method

At a pitch of one millimetre and above, which covers ordinary processors and programmable logic, a diagonal escape with a through via is normally sufficient on a four layer board. At nought point eight millimetres, found on mid range devices and memory, the diagonal escape continues to work with a blind or a through via on four to six layers.

At nought point six five millimetres, the geometry no longer allows a straight route between the balls, and the signal escapes through a short dog bone structure with the via placed beside the pad, on six to eight layers. At nought point five millimetres, the laser drilled blind via becomes the practical route, and eight or more layers are usual.

At nought point four millimetres, the hardest of the common pitches, neither a through via nor an ordinary blind via fits inside the space available. The two working answers are a first order high density interconnect structure, in which a laser blind via of around nought point one millimetres passes between the balls, or a via in pad structure, in which the via sits directly on the pad and is filled and plated flat.

Escaping from a 0.4mm Array

The first order high density interconnect approach is the more widely used, because the process is established and the cost is controlled. The blind vias are drilled by laser from the outer layer to the first inner layer, and the routing from the outer ring of pads takes place on the layer immediately beneath the device. The diameter of the via is small enough to pass between two balls of the array, which is what makes the escape possible at all.

The via in pad approach is used where the pin density is higher still and the routing resources under the device are exhausted. The via occupies the centre of the pad, so no space beside the pad is needed, and the barrel is filled with resin and plated flat so that the ball can be soldered to a level surface. The cost is higher because of the extra process steps, and the decision is made from the pin count and the available routing rather than from the pitch alone.

A mixed approach is common on a real board. The outer two rows are escaped on the outer layer, the inner rows use laser vias, and the power and ground balls are connected directly to the planes beneath through their own vias, which removes a large part of the routing problem before it starts.

The Other Design Decisions

The pad size is taken from the package drawing and the relevant standard, with the soldering yield and the reliability of the joint in mind rather than only the space available. A pad that is made smaller than the drawing allows to gain routing space reduces the area of the joint and the adhesion of the pad to the laminate.

Via size and spacing are set from what the fabricator can produce. A via that the fabricator cannot drill to the required tolerance is not a routing resource, and a design that assumes otherwise is returned at the cam stage. For this reason the routing rules are agreed with the fabricator before the escape is drawn rather than after.

Impedance control applies to the high speed pins just as it does elsewhere on the board. The choice of reference plane and the treatment of the via stub affect the quality of the signal, and a long stub left on a via creates a resonance that shows up at the frequencies the interface uses. Where the layer count allows, the via is back drilled or the signal is routed on a layer that keeps the stub short.

Testability is the fourth decision, and it is often the one that is left until too late. Test points are reserved where they can be reached, or a boundary scan method is planned instead, so that the joints under the package can be verified by X-ray or by the device itself rather than assumed to be sound.

How the Design Work Is Sequenced

The package data and the schematic are received first, and the pitch, the pin count and the signal rate are assessed to establish the layer count and the escape method. The stack-up is then planned from the number of signals and the impedance requirement, which fixes the positions of the ground and power layers and the signal layers between them.

The escape is drawn next, together with the length matching, the impedance control and the shielding that the high speed signals require. A design rule check follows, and the release goes through three levels of review: the engineer who drew it, the project lead, and a senior engineer, before the files are delivered. That sequence is what keeps a dense design from arriving with a problem that only appears at the fabricator.

Capability and the Deliverables

Designs are accepted down to a pitch of nought point four millimetres, including chip scale packages, and packages with more than two thousand pins have been designed. The escape methods covered include through vias, blind and buried vias, high density interconnect and via in pad. High speed interfaces such as memory, serial links and USB are part of the routine work, and the design group includes more than fifty engineers with a volume of more than two thousand boards a year.

Designs are delivered as the source file and the production package, and because the same group also manufactures and assembles, the design and the process are not separated. A question about what the fabricator can hold, or about how the assembly line will support the board, is answered by the people who will do the work rather than by a message between companies. Our PCB design and layout group carries out the work, PCB manufacturing produces the high layer count and high density boards, and SMT assembly places the devices.

FAQ

How many layers does a ball grid array design need? An ordinary package at one millimetre pitch can be escaped on four layers. A mid range device at nought point eight millimetres usually needs about six, and a dense device at nought point four millimetres generally needs eight or more on a high density board.

Does a nought point four millimetre pitch always require a high density board? In almost every case it does, because a through via with its annular ring is wider than the space between two balls.

How are the power pins handled? They are connected directly to the planes beneath the device through their own vias, which shortens the loop and reduces the area that has to be found on a signal layer.