High-Speed Routing on Multilayer PCB: Stackup and Rules

Speed changes the rules of layout. At low frequency a trace is a wire; at high frequency it is a transmission line, and its behaviour depends on the structure around it rather than on the netlist. High-speed routing is the practice of designing that structure deliberately, and on a multilayer board it starts with the stackup rather than with the first trace.

Choose the Stackup From the Frequency

The layer count should be a consequence of the signalling, not a purchasing decision made in advance. A rough working guide is useful even though the real boundary depends on edge rates, board size and routing length.

Four layers suit moderate signalling — clock frequencies up to roughly five hundred megahertz — and the conventional arrangement is a signal layer, a ground plane, a power plane and a second signal layer. Two plane layers give every signal a reference, which is the property that makes the arrangement work.

Six layers carry designs in the five hundred megahertz to one gigahertz range. A typical sequence is signal, ground, signal, power, ground, signal: the two ground planes provide references to the signal layers on either side of them, and the inner signal layer is shielded from the outer ones.

Eight layers and above are used for signalling at or above a gigahertz, and for boards where the routing channel count alone forces the extra layers. At this level the stackup is designed around the critical nets: which layer each interface is routed on, and which plane it references there.

The governing rule is simpler than the table. Critical signals — clocks, high-speed buses, differential interfaces — should be routed on layers adjacent to a complete ground plane. That adjacency gives the signal a defined reference, keeps the return current directly beneath the trace, reduces loop area, and is the foundation of both impedance control and lower emissions. How those layer decisions are made in practice is covered in this discussion of multilayer layer assignment.

Hold the Impedance Constant

A high-speed signal reflects wherever it meets a change in characteristic impedance, and reflections close the eye at the receiver. The design objective is continuity from driver to load.

That means keeping trace width and dielectric height consistent along the whole path, and — more often forgotten — keeping them consistent through transitions. A signal that changes layer passes through a via, and the via’s geometry is a discontinuity unless it is designed as one of a set: similar via size, similar antipad, similar distance to the reference plane. Where the impedance does have to change, the change should be deliberate and accounted for in the simulation rather than discovered on the test bench.

Route With the Physics in Mind

Traces should be as short and as straight as the design allows. Every bend is an opportunity for a discontinuity, and where a turn is unavoidable, an angled or curved route behaves better than a sharp right angle, which presents a localised change in effective width at the corner.

Vias deserve particular attention. Each one adds parasitic capacitance — commonly quoted as around half a picofarad for a standard through via — and each one also adds inductance from the barrel that is not part of the driven path. High-speed links therefore minimise via count, and where a via is necessary, the choice between through, blind and buried structures is made on electrical grounds as well as density grounds. For very fast interfaces, unnecessary barrel length below the layer being used has to be removed or terminated so that the via stub does not resonate at a frequency inside the signal bandwidth.

Isolate and Shield

High-speed nets should not be routed through low-speed regions, and low-speed or switching nets should not be routed through the region occupied by a high-speed interface. Where they must coexist in the same area, a ground plane between the relevant layers provides the separation, since the plane carries the return current for both and prevents fields from coupling between them.

The same principle applies within an interface. A differential pair needs its two traces to be treated as a pair; a clock line, being one of the strongest emitters on a board, should be routed close to its reference plane and must not run parallel to unrelated signals for any distance, because parallel runs couple.

Treat Clocks and Differential Pairs Separately

Clocks are periodic, which means their energy is concentrated at specific frequencies and their harmonics, and they radiate efficiently. Route them as directly as possible, reference them to a solid plane at every point, and keep them away from connectors and board edges where radiation escapes and external fields enter.

Differential pairs depend on symmetry. The two traces must be the same length and the same distance apart for the whole run, must see the same dielectric environment, and must arrive at the same pin geometry, because any asymmetry converts part of the differential signal into a common-mode component — which is precisely the part that radiates and that the receiver rejects least effectively. Length matching within a pair and, where the interface requires it, across a group of pairs, is a design target rather than a finishing step.

Simulate Before You Commit

At high speed, the layout cannot be validated by inspection. Simulation is used to examine signal integrity and electromagnetic behaviour, and its results feed back into the stackup, the layer assignment, the terminations and the via design. The cost of that work is a fraction of the cost of a respin, which is why it sits inside the design loop rather than at the end of it.

For dense interfaces, the same discipline extends into package and device fanout, as described in these notes on high-speed FPGA PCB design.

What This Looks Like in Products

Communications equipment, servers and aerospace systems are the habitual users of high layer counts, because they combine many fast interfaces on one assembly. A handset main board may be built on four or six layers, while a router board may need eight or twelve, and the difference follows from the number and speed of the links that must be supported simultaneously.

In every case, the layout determines whether the design works. The same components and the same netlist can be routed into a board that passes compliance testing and one that fails it, and the difference lies entirely in the structure: which layer each signal uses, what it references, and how carefully the transitions were designed. Where the routing demands finer features than a conventional stackup provides, those constraints are handled in the ways described in this review of impedance control through the design flow.

FAQ

Does a four-layer board count as high speed? It can be, provided the two inner layers are used as ground and power planes and the signalling stays within what a four-layer stackup can support. A four-layer board used as two signal and two spare layers is not a high-speed stackup at all.

Why is a via a problem if the signal reaches the other side? Because it reaches the other side through a structure with capacitance to the planes it passes and inductance in its barrel, and because any barrel length beyond the destination layer forms a stub that can resonate within the signal bandwidth.

Is length matching always required for differential pairs? Matching matters most where the pair is part of a timing-critical interface. A small mismatch on a short pair at moderate speed is often tolerable, but the tolerance should come from the interface specification rather than from convenience.