Layer Assignment in Multilayer Boards: Power, Ground and Signal

Layer assignment is the part of multilayer design that is hardest to change later. Once the stack-up is fixed, the impedance of every controlled trace is fixed with it, the reference plane each signal returns through is decided, and the space available for routing is a known quantity rather than a hope. Getting it right is mostly a matter of deciding what each layer is for before anything is drawn on it.

Start From the Supplies

The first question is how many separate supplies the board carries, because each of them needs somewhere to go and each of them interacts with the others.

Supplies at different voltages should be given separate regions rather than being interleaved. Placing a lower-voltage region at one end of the board and a higher-voltage region at the other reduces the coupling between them and makes the return paths for each unambiguous. Where a supply feeds only one area of the board, keeping its copper local to that area is usually better than running it across the whole panel.

The width of the copper matters more than its shape. A power region that is broad and continuous presents low impedance and low inductance, which is what the load needs at the frequencies where the regulator can no longer respond. Narrow necks between wide regions are the places where the supply impedance rises and where noise from one part of the board reaches another.

Planning the Power Plane Regions

A power plane is not merely a large piece of copper. Three decisions define it.

The first is the shape. Regions should be drawn to follow the circuits they serve, so that current does not have to travel a long way around an obstacle. Long detours add inductance, and inductance is what turns a load transient into a voltage excursion.

The second is the interface between regions. Where two supplies must cross or run alongside each other, the clearance between them should be as generous as the space allows, because the capacitance between two adjacent copper regions couples noise from one supply into the other. Where the spacing cannot be large, a grounded region between them is an effective barrier.

The third is decoupling. Capacitors belong at the point of use, close to the pins they serve, and the plane is the path that connects them to the source. A capacitor placed far from its load is connected by the plane’s inductance, which is the quantity the capacitor was added to manage.

The Ground Plane

The ground plane is the reference for every signal on the board and the return path for every current, and that dual role is why the plane should be treated as the most important layer rather than the leftover one.

The general principle is a single continuous plane. A plane that is cut into pieces forces return currents to detour around the cuts, and those detours are loops: they radiate, they receive, and they change the impedance of the traces above them. Where a plane must be divided — to separate a noisy digital ground from a sensitive analogue one, for example — the division should be deliberate and the two sections joined at a single defined point, so that the potential difference between them is bounded and known rather than developing wherever the two sections happen to overlap.

Pairing the ground plane with a power plane is equally important. Two planes separated by a thin dielectric form a capacitance distributed across the board, which supplies current at frequencies where discrete capacitors have become ineffective. That is why the ground and power layers are placed adjacent to each other in most well-designed stacks, and why the distance between them is kept as small as the fabrication process allows.

Assigning the Signal Layers

Signals are assigned by type, not by convenience.

Fast signals — clocks, high-rate data buses and anything with a controlled impedance requirement — should have layers whose position in the stack was chosen for them. That normally means a signal layer adjacent to a plane, so that each trace has a continuous reference directly beneath it, and it means keeping such signals off layers where the reference is interrupted or where the routing must cross from one reference to another.

Ordinary signals are then arranged by flow. Ordering them so that the connections between a group of components stay on one layer, rather than passing through several, reduces the number of vias, shortens the paths and keeps the return paths simple.

Spacing between traces follows the signal rather than a blanket rule. The isolation a trace needs depends on its rate and on its voltage, and applying the strictest spacing everywhere wastes area that faster nets could use.

How the Layers Relate to Each Other

Three relationships do most of the work.

A signal layer next to a plane layer is the fundamental pairing, because it gives every trace on that layer a return path directly beneath it. Two signal layers next to each other, with no plane between them, allow the traces on one to couple into the other, and if they run parallel over any distance the coupling is significant.

Where two signal layers are necessarily adjacent, their routing should run in different directions, so that traces cross rather than run alongside. This is a layout decision, but it is only possible if the layer assignment anticipates it.

And signals should avoid changing reference planes unnecessarily. Every layer change is a point where the return current has to move from one plane to another, and unless a via is provided for that current close to the signal via, the return path takes a detour that damages the signal and radiates.

Symmetry and Mechanical Balance

Layer assignment also determines whether the finished board stays flat.

A stack that is symmetric about its centre — the same construction on each side, with copper balanced between the layers — presses with less internal stress than one that is heavier on one side. That symmetry is a property of the assignment, not of the routing, so it has to be decided at this stage; correcting an unbalanced stack after the fact means changing the construction, which changes every impedance on the board.

The same reasoning applies to copper distribution within a layer. A layer with a large plane on one side and almost nothing on the other will behave differently from a balanced one during pressing and during the thermal excursions of assembly. The mechanisms behind this are described in the article on PCB warpage.

Checking the Assignment

The review of a finished stack-up is a short list of questions. Does every controlled-impedance signal have a plane adjacent to it and a return path that stays beneath it? Are the power regions sized for the current they carry, with no narrow necks at the points of highest demand? Is there a continuous ground reference for the analogue section, and is it joined to the rest in one place? Is the stack symmetric? And is there enough routing space on the signal layers assigned, or will the design force additional layers — which is a much more expensive answer at this stage than at any other?

Where the assignment supports fast signals, the questions extend to the electrical behaviour. The effect of a split plane on a signal that crosses it, and the way an impedance change produces a reflection, are described in the note on the reflection coefficient and impedance, and the way a reference plane supports the return current of a high-speed signal is covered in the article on high-frequency routing. Our quality management overview describes how these checks fit into the wider process.

FAQ

Should every signal layer be adjacent to a plane? Ideally. Where a design cannot afford that, the adjacent signal layers should be routed orthogonally so that their traces cross rather than run parallel.

Why keep the power and ground planes close together? Because the thin dielectric between them forms a capacitance distributed across the board, which provides current at frequencies where discrete decoupling capacitors no longer respond quickly enough.

Can the stack-up be changed after routing? Only at the cost of re-tuning every controlled impedance and re-checking every return path. It is the most expensive change a design can make, which is why it is settled first.