Skew and Jitter Sources in High-Speed PCB Design

Skew and jitter are often discussed as if they were the same thing and as if they had a single cause. In practice the total timing error on an interconnect accumulates from several independent sources, and only one of them is the fiber weave of the laminate. Fiber weave skew is real, but treating it as the whole problem leads to length matching that does nothing for the rest of the error budget. A complete view starts with a list of sources and their signatures.

Random and Deterministic Timing Error

Random timing error comes from thermal noise. It is unbounded in theory but small in practice, and it only matters in very precise low-level measurements. Deterministic timing error has an identifiable cause and a bounded magnitude, and it is what most high-speed links have to budget for. Skew between two conductors and jitter on a single conductor are both usually deterministic in origin.

Separating them matters because the remedies differ. Skew between the two halves of a differential pair is corrected by length matching. Jitter caused by supply noise is corrected by power integrity work. Applying length matching to a problem caused by supply noise simply consumes routing resources without improving the margin.

Source One: Fiber Weave Skew

Laminates are built from woven glass cloth, and the weave is periodic. Where a trace runs along a bundle of fibers, its effective dielectric constant is higher than where it runs over a resin-rich window between bundles. Two traces of identical length can therefore have different propagation delays, and the difference grows with the length of the pair. The standard remedies are to use spread glass, to route the pair at an angle to the weave, and to keep both halves of a differential pair on the same layer so they see the same material.

Fiber weave skew is proportional to length, so it is mainly a problem on long backplane-class channels. On short links inside a card the effect is usually smaller than the other sources on this list.

The remaining sources are mostly system-level effects that arise from the interaction between the chip, the package and the board.

Source Two: Supply-Induced Periodic Skew

Switching of high-speed input and output buffers injects current into the supply network, which modulates the supply voltage seen by the drivers. That modulation shifts the switching threshold and moves the crossing point of the output waveform, which appears as periodic timing error at the receiver. The remedy is power integrity work: adequate decoupling at the right frequencies, low-impedance plane pairs, and a supply distribution that does not share inductance between banks.

Periodicity is the signature to look for. If the timing error repeats at the rate of known switching activity, supply noise is the likely cause, and no amount of trace matching will remove it.

Source Three: Crosstalk-Induced Skew

Coupling from an aggressor net onto a victim shifts the victim edge. The effect is uncorrelated with the victim data, so it looks like random noise even though it is deterministic. The magnitude depends on the coupling length, the spacing and the edge rate of the aggressor. Widening the spacing, shortening parallel runs and providing a continuous reference plane are the direct remedies, and spacing guided by the 3W crosstalk rule is a reasonable starting point.

Source Four: Duty Cycle Distortion

Duty cycle distortion occurs when the switching threshold of a driver or receiver is offset from its ideal value. The rising edge and the falling edge are then displaced in opposite directions, and the pulse width at the receiver changes. The cause can be an asymmetric driver, an offset in the receiver, or a common mode shift on a differential link. It is measured as the difference between the two eye crossings, and it consumes timing margin directly.

Source Five: Inter-Symbol Interference

Reflections from impedance discontinuities, together with channel dispersion, cause one symbol to disturb the symbols that follow it. A reflected edge can advance or delay the edge of the next symbol, so the error depends on the data pattern. This is why timing measurements must be made with a pattern that exercises the worst case rather than with a simple clock. Removing reflection sources such as vias, connectors and impedance discontinuities is the main line of defence.

Source Six: Data-Dependent Pulse Width

A bandwidth-limited channel changes the width of a pulse as a function of the data pattern. Dielectric loss, skin effect, termination dispersion and parasitic capacitance all contribute. The signature is a pulse width that varies with the run length of identical bits. Transmitter pre-emphasis or receiver equalization are the practical remedies, and their settings have to be derived from the actual channel rather than from a template.

Because the sources are independent, the response has to be organised rather than improvised.

What Cannot Be Removed

Not all skew can be eliminated. Even with every deterministic source suppressed, thermal noise leaves a small random component that no layout can remove. The realistic goal is to reduce the deterministic sources to a level where the remaining budget is comfortably positive, and to confirm that the receiver still has margin in the worst-case pattern and at the temperature extremes.

Layout Practices That Reduce Total Skew

Start with the material. Spread glass, or an angled routing direction relative to the weave, addresses fiber weave directly. Then control parasitic coupling as part of high-frequency trace and data bus routing, by planning the stackup so every high-speed layer has a solid reference plane nearby, and by keeping aggressor nets away from sensitive ones. Termination should be designed so the impedance is flat across the bandwidth the channel actually uses, which means matching the termination to the channel rather than to the nominal impedance alone.

Power integrity comes next, because components that need precise timing should see a stable supply. Only after those steps does conventional delay tuning apply. Serpentine routing for length matching compensates the residual mismatch between conductors, and it works best when the tuning sections are kept compact and spaced so they do not introduce new coupling of their own.

Verification

A timing budget is only useful if it is checked. Time-domain reflectometry and transmission measurements characterise the channel, and eye diagram measurements under the worst-case pattern show the residual margin. Because the sources are independent, their contributions add in a root-sum-square sense rather than linearly, and a measured total that agrees with that prediction is evidence that the source list is complete.

Where the measurement disagrees, the difference is itself diagnostic. A larger than predicted error usually points to a coupling path that was not in the model, such as a connector, a package transition or a shared return path between two signal groups.

FAQ

Is fiber weave skew worth worrying about on a normal board? Only on long links. It scales with trace length, so it matters on backplane channels and long cable-side runs, and is usually negligible on short intra-board connections.

Can length matching fix supply-induced jitter? No. Length matching corrects differences in propagation delay between conductors. Jitter caused by supply noise has to be reduced by improving the power delivery network and the decoupling.

Which source contributes most in practice? It depends on the channel. Crosstalk and inter-symbol interference dominate on dense boards with long parallel runs, while supply noise dominates where many outputs switch simultaneously.