High Frequency Traces and Data Buses: Layout Rules

Almost every layout guide repeats the same advice: keep digital and analogue grounds separate. Anyone who has laid out a real board knows how difficult that is to achieve in practice, and the reason is that the advice describes a conclusion rather than a method. The method starts earlier, with an understanding of what each device on the board actually does electrically.

Understand the Devices Before Routing

A designer has to know a few things about every integrated circuit being placed. Which pins generate harmonics — in practice, the outputs and switching nodes whose edges are steepest. Which pins are susceptible to induced interference. And, where the manufacturer provides it, the internal signal flow diagram, since knowing how the part processes signals explains both of the previous points.

The overall layout of the product decides electrical performance before any trace is drawn, and the board-level portion of it is mostly about the flow of signals and data between devices. Two principles cover most cases. Circuits that radiate strongly should be placed near the power section, where the supply and its return are closest. Weak-signal processing should be positioned as close as possible to the signal input or the sensor, which is usually fixed by the mechanical design of the product — and placing it there improves the signal-to-noise ratio, which in turn gives the downstream processing a cleaner signal and more reliable data.

Two Kinds of Signal, Two Kinds of Trace

Copper width is not a single answer. Modern digital clocks are fast enough that the assumption behind the familiar rules no longer holds, and the two categories have to be treated separately.

High frequency traces should be narrow rather than wide, and short rather than long. A wide conductor behaves well on a low-frequency, high-current path, but at high frequency the current no longer distributes itself evenly across the cross-section — it concentrates near the surface, which is the skin effect. That makes a wide trace a liability rather than an asset, and the longer the trace, the more opportunity it has to couple to its neighbours, which is really a placement problem that shows up as a routing problem. Keeping these traces narrow and short reduces induced electromagnetic interference.

Data signals need a different emphasis, because they are carried as pulses and it is their harmonic content that determines whether the receiving circuit recognises the data correctly. A wide copper conductor also suffers from skin effect, and its distributed capacitance and inductance are larger, so the signal degrades and the data can be misread. There is a second effect that is easy to miss: if the widths of the conductors within a data bus differ, their delays differ, and the bus loses synchronisation.

That is why serpentine routing appears in data buses. The technique exists to make the delays of the individual lines more nearly equal, so that the bits of a word arrive together rather than spread out along the bus.

Copper Pour and Its Limits

Large-area copper has a specific purpose: shielding against interference, and reducing susceptibility to induced interference. Its electrical role is not to carry signals.

On a two-layer board, a ground pour can serve that shielding function, which is one of the reasons the technique was discussed earlier in this look at copper pour on outer layers. On a multilayer board the question is largely already answered: the power and ground planes inside the stack do the shielding and isolation work by themselves, and an additional outer-layer pour adds much less than it would on a two-layer design.

Layer Order on a Four-Layer Board

For a four-layer board, the conventional and effective arrangement is to place the power layers — positive and negative — in the middle, and to route signals on the two outer layers. One rule accompanies it: no signal layer should sit between the positive and negative power layers.

That arrangement lets the power layers do their filtering, shielding and isolating work as fully as possible, because they are adjacent to the signal layers that need referencing and separated from each other only by dielectric. It is also easier for the fabrication house to build, which improves yield. The reasoning behind such arrangements is developed further in this discussion of multilayer layer assignment.

Via Design

Vias should be minimised. Each one adds capacitance to the net it carries, and each is a place where burrs can form — and a burr is a small radiator.

For electrical performance, a smaller via size is generally better than a larger one. Smaller holes produce fewer burrs after copper deposition than large ones, a consequence of the drilling process itself. But a hole can be too small to manufacture reliably, so the common sizes in practice are 0.5 millimetres and 0.8 millimetres, with 0.3 millimetres used sparingly and only where the density demands it.

The trade-off between electrical benefit and manufacturability is the same one that governs via selection in general, and the rules involved are set out in this discussion of via design rules.

<img src="https://www.gopcba.com/wp-content/uploads/2026/05/Industrial-IOT-1.jpg" alt="serpentine routing used to match data bus delays” />

Software and the Fabrication Package

Tool choice matters less than familiarity with it, which is worth stating because layout advice is often given as tool advice. For simple circuits whose behaviour the designer already understands, routing directly from a mental model is efficient. For complex designs and unfamiliar devices, drawing the schematic first and working from a netlist is both more correct and more convenient.

One practical case is worth noting. Non-circular holes — slots and cut-outs — often have no dedicated function in layout software. A workable habit is to create a dedicated layer for such features, draw the hole shape on it and fill the drawing so that the outline is unmistakable, then explain it explicitly in the documentation sent with the board.

When the board is released for prototyping, the package should include the board file itself; a documented list of what each layer contains, because conventions differ between engineers and the fabricator cannot guess which layer is silk, mask, copper or mechanical; the process requirements, including surface finish, board thickness and whether the laminate is flame retardant; the quantity required; and contact details for whoever can answer questions about it.

The list looks administrative, but it prevents the most expensive category of error in prototyping — a board that was fabricated exactly as specified, against a specification nobody intended. The trace dimensions that such a package has to state are derived as described in this note on trace width calculation.

FAQ

Why should high-frequency traces be narrow rather than wide? Because at high frequency current concentrates near the conductor surface, and a wide trace increases the area available for coupling to neighbours. Narrow and short minimises both the skin-effect penalty and the induced interference.

What is serpentine routing for? It is used in data buses to equalise the delay between individual lines, so that all the bits of a word arrive at the receiver together instead of spread across a timing window.

Why avoid a signal layer between the power layers? Because it interrupts the pair of planes that do the filtering, shielding and isolating work. Keeping the planes adjacent to each other and to the signal layers preserves the benefit and makes the stack easier to build.