Good PCB Design Practice: Noise, Impedance and Clock Routing

Connecting every net so that the board passes a continuity test is the beginning of layout, not the end of it. The difference between a board that works on the bench and one that works everywhere is made up of a handful of practices that are applied on the nets where they matter. The notes below collect the ones that repay the effort most consistently, and each of them has a mechanism behind it rather than a rule to be followed blindly.

Know the Devices and the Interfaces

Good PCB design starts with understanding what the components do, how they influence one another, and what the interfaces between them actually require. A designer who knows the data standard behind a bus will place and route it differently from one who treats it as a group of wires. The same applies in the other direction: a schematic designer who understands layout constraints tends to produce a design that is easier to implement, because the partitioning and the interface choices are made with the physical consequences in mind. The two roles are separate but the knowledge overlaps, and the overlap is where most avoidable problems are eliminated.

Switching Noise, Ringing and Crosstalk

As edge rates increase, several effects appear at once: simultaneous switching noise, ringing, crosstalk, ground bounce and supply noise. They have different causes and therefore different remedies, and treating them as one problem leads to fixes that do not work. Ringing and crosstalk are the pair that most often affects a critical net, and the standard answer is differential signalling. Routing a critical signal as a differential pair removes the dependence on a single-ended reference and reduces the induced current in the return path that produces bounce. The pair should be routed as a pair, with matched length and a continuous reference plane, so that the coupling between the two conductors is defined by geometry rather than by whatever else is nearby. The geometry that preserves the balance of a pair through a bend is described in this article on right-angle routing in differential traces.

Impedance Matching

Impedance matching is not only an RF concern. A differential pair is commonly designed for a characteristic impedance of 100 ohms, which has become an industry standard value for high-speed differential links, and the pair is built from two single-ended lines that would each be 50 ohms in isolation. Because the two conductors are close together, the field coupling between them lowers the differential impedance of the pair, so the width of each line has to be reduced slightly to bring the pair back to 100 ohms. A consequence worth remembering is that the common-mode impedance of each conductor in such a pair ends up slightly above 50 ohms. The practical lesson is that the numbers on a datasheet describe a physical geometry, and the geometry should be agreed with the fabricator, who knows the dielectric thickness and the copper weight that will actually be used. Asking a fabricator which impedances it can hold for a given stackup is faster than deriving them and discovering that they cannot be built.

Decoupling and Bypass Capacitors

Decoupling and bypass capacitors perform related but distinct functions. A decoupling capacitor reduces the inductance between the supply and ground planes and controls the impedance seen by the signals and devices on the board. A bypass capacitor provides a local reservoir of charge so that a device drawing a fast transient current does not have to obtain it from the far end of the board. Both are placed close to the device they serve, and the connection is the part that matters: a capacitor connected through a long trace or a via stub has already lost most of its benefit before the transient arrives. This is why the placement of a decoupling capacitor should be decided during placement rather than at the routing stage, and why the general habit of placing them wherever the layout is convenient is a poor guide.

Layout: The Shortest and Most Direct Path

The most useful single principle in layout is that the best connection is the shortest and most direct one. A short path has less resistance, less inductance, less coupling to its neighbours and less opportunity to pick up interference. It is also easier to keep within a timing budget. Applying the principle does not mean routing everything in a straight line, since mechanical constraints usually prevent it, but it does mean preferring the direct option whenever the choice exists, and treating a detour as something that has to be justified rather than as a normal part of the layout.

Clock Signal Handling

Clocks deserve their own set of practices, because jitter and skew introduced by the clock propagate into every downstream device and are amplified as the clock frequency rises. The first requirement is to keep the clock trace short and to avoid routing it across other signals. Layer changes should be avoided on clock nets, because a via introduces an impedance discontinuity and a reflection that shifts the arrival time. Where the clock must run on an inner layer, the layers immediately above and below should be ground planes, which gives the trace a defined reference and reduces the delay variation caused by other routing. If supply noise is reaching the clock generation circuitry and increasing phase-locked loop jitter, the layout can be changed to create a power island: a region of the plane separated from the main supply so that the analog supply of the clock circuit and the digital supply of the rest of the device do not share a noisy reference. The plane structures that make this possible are described in this article on power plane splitting rules, and the via practices that keep a clock net clean are covered in this article on via design rules.

Use the Reference Design, but Understand It

Device vendors publish reference designs for their processors and controllers, and they are a valuable starting point. The layout of the critical sections, the placement of the supply components and the routing of the memory and clock nets are usually the result of the vendor”s own validation work, and following them reduces the risk of a fundamental error. The caveat is that a reference design is usually built to demonstrate several use cases at once, so it may not match the requirements of a particular product. The right approach is to use it as a baseline for the sections it covers, to understand why the layout was done that way, and to depart from it deliberately where the product requires something different, rather than copying the geometry without knowing what it protects against.

FAQ

Why does a 100 ohm differential pair use narrower traces than two 50 ohm lines? Because the proximity of the two conductors reduces the differential impedance, so the width has to be reduced to bring the pair back to its target value.

Should every net be routed as a differential pair? No. Differential routing is used where it removes a problem, typically on critical high-speed nets, and applying it everywhere wastes routing channels without benefit.

Why avoid vias on a clock net? Because each via changes the impedance and reflects part of the signal, which shifts the arrival time and adds jitter that downstream devices amplify.