Via Design Rules: Sizes, Spacing and Fanout

Vias are the cheapest way to add a layer’s worth of routing, and they are also one of the largest single contributors to the cost of a board: the drilling and plating operations behind them account for a large share of what a fabricator charges. That makes via design a place where performance and cost meet directly, and where a few standard decisions prevent most of the problems vias cause.

Choosing the Size

A via consists of the drilled hole and the copper land around it, and both dimensions are bounded by what the process can hold.

The drill diameter has a practical minimum. Below a certain diameter the drill deflects more easily, so the hole lands off centre, and the aspect ratio — the depth of the hole divided by its diameter — rises to the point where plating the barrel uniformly becomes unreliable. The rule of thumb is that once the hole is more than about six times deeper than it is wide, uniformity suffers.

The land around the hole has its own minimum, since it has to absorb the positional tolerance of both the drill and the artwork. A common working relationship is that the outer diameter is roughly twice the hole diameter, within a small tolerance, so a hole of one size maps to a small set of acceptable land sizes. Shrinking the land below the fabricator’s minimum does not remove the risk; it moves it into the finished board, where a breakout is a defect rather than a design decision.

On fast nets there is a reason to prefer the small end of the range, because the capacitance of the land to the reference plane loads the signal. The correct approach is to use the smallest size the fabricator confirms it can hold, rather than the smallest size the design tool allows.

Blind and Buried Vias

Blind and buried vias increase the routing density by connecting only the layers that need connecting, and they cost far more per hole because they require additional lamination and drilling cycles. The cost does not rise linearly with the number of cycles; it rises steeply, because each cycle adds process steps and reduces yield.

A practical position is to avoid them entirely where a through via can do the same job. Where a package pitch forces the issue, a single build-up level — a blind via from the outer layer to the layer beneath, and the same on the other side — is usually the sensible compromise, and higher-order stacks are reserved for designs where the density genuinely cannot be achieved any other way. The relationship between the structures and the fabrication sequence is described in the article on HDI blind via fabrication.

Vias Near Pads

Placing a via directly in a pad shortens the connection and removes inductance, and it also creates two risks.

The first is solder loss. The barrel is open at the pad surface, and during reflow the paste can flow into it, leaving the joint with less material than the design intended and, on a small chip component, an imbalance between the two ends that produces a component standing on one end.

The second is that the via interrupts the copper structure around the pad in ways that are not always accounted for, particularly when the pad sits over a plane.

Where the via cannot be moved, it should be filled and capped so that the pad surface is flat and closed, and the panel should be inspected for the joints above those vias with a method that can see under the component rather than from above. Where the via can be moved, a clearance of a few thousandths of an inch between the via and the pad edge keeps the paste where it belongs, and it is usually possible with a small adjustment to the fanout.

Inside a ball array the situation is different. The via normally sits at the centre of the pad, and the requirement is that it is genuinely centred rather than offset, because an offset via reduces the pad area on one side and can lead to bridging. Filling and capping is standard in that position. The details of this case are covered in the note on via in pad for fine-pitch BGA, and the cost of the filling process, together with the situations in which it can be avoided, is examined in the article on replacing via in pad.

Via Spacing

Vias placed too close together cause two problems that appear at different stages. Drilling one hole near another weakens the material between them and can cause the laminate to break out between the two, which is a defect that cannot be repaired. If the holes are close enough for their lands to overlap, the copper between them is removed and the connection between the two vias is no longer defined by the design.

A workable minimum spacing is around half a millimetre between centres. Below that the risk rises quickly, and very tight spacings should not be used at all. In dense areas the better answers are to stagger the vias so that no two are adjacent on the same axis, to reduce the diameter where the design permits, and to reconsider whether the fanout pattern is the most economical one for the layer budget — because adding a layer is often cheaper than forcing vias into a pattern the process cannot hold.

Tenting and Plugging

Covering the via with solder mask — tenting — is the usual treatment for small vias, and where a via must be closed against solder it is filled and capped instead.

The cases where closing is required are specific. A via beneath a component with a metal body has to be closed, because an open barrel can short to the case. A via in a pad has to be closed, for the reason described above. And a via that sits where flux or cleaning fluid could be trapped should be closed so that the residue does not remain in the board and cause corrosion later.

The exception is the thermal via. Where a cluster of vias exists to carry heat from a device to copper below it, leaving them open is often preferable because it exposes more copper surface to the airflow. The decision should be stated explicitly in the fabrication data, since it is the opposite of the default treatment.

Vias as Mechanical Reinforcement

Some pads carry mechanical load as well as electrical connections: the pads of a connector, the terminals of a switch or button, the contacts where a flexible circuit is bonded. These pads are subjected to force every time the product is used, and the copper that anchors them to the laminate is what resists that force.

Adding a small number of vias near those pads increases the copper’s grip on the board and distributes the load into the layers beneath, rather than concentrating it at the laminate surface. It is a small addition and it addresses a failure that is otherwise discovered in the field, after the pads have begun to lift.

Fanout Strategy

The way vias are arranged around a component determines how much routing the inner layers can carry.

For two-terminal chip components, the vias belong outside the pads, on the side away from the component body, so that the inner layers can be routed between the two vias. Vias placed between the pads instead create a barrier that the inner-layer routing has to go around, and they interrupt the reference plane beneath the component.

For a ball array, the constraints are the pitch and the number of rows that must be escaped. The first rows are escaped directly; further in, the routing runs between the balls on an inner layer and the vias move outwards in a pattern that keeps the plane as continuous as the density allows. Cutting the plane is sometimes unavoidable, and where it happens the design should provide a return path for signals that cross the split.

Both patterns belong to the review rather than to the routing alone. Our layout quality checklist covers the via items that are most often missed.

FAQ

How small can a via be? It depends on the fabricator and on the aspect ratio. The practical limit is set by how reliably the barrel can be plated at that diameter through the board’s thickness, not by the drill alone.

When should vias be filled? Whenever the barrel would otherwise be open where solder, flux or a metal component body could reach it. Thermal vias are the usual exception.

Why place fanout vias outside chip pads? So that inner-layer routing can pass between them and the reference plane beneath the component stays as continuous as the stack allows.