PCB Routing Guide: Trace Width, Spacing and Return Paths

Pcb routing is the stage where a schematic becomes physical copper, and it is where most of the electrical performance of a board is actually decided. Placement sets the possible solutions and the stackup sets the impedance, but the path each net takes determines whether the design survives its first functional test. Treating routing as a purely geometric exercise to be finished quickly is the most common cause of a second prototype.

Routing Comes After Placement, Not Before

Routing can only be as good as the placement that precedes it. If the decoupling capacitors are far from the pins they serve, no amount of careful trace work will recover the impedance. If a connector faces the wrong way, every net leaving it acquires unnecessary length. The correct sequence is to finish placement, review it against the critical nets, and only then begin routing.

The same is true of the layer assignment. Deciding which layer carries the high speed bus, which layer carries the ground reference and where the power pours will sit determines what routing is possible. Attempting to route first and assign layers afterwards almost always produces a board where the return path for a fast signal is discontinuous.

Return Paths Decide Signal Quality

A signal travels out along its trace and back along a reference. At high frequency the return current does not take the lowest resistance path, it takes the lowest inductance path, which means it flows directly beneath the signal trace in the adjacent plane. Where that plane is interrupted, the return has to detour, and the detour adds inductance and creates a radiating loop.

The practical rule is simple: never let a fast signal cross a gap in its reference plane. That includes gaps created by plane splits, by connector cut-outs and by rows of via holes that clear the plane. Where a crossing is unavoidable, provide a stitching capacitor or a bridge of copper next to the crossing point so the return current has a local path, following the approach in power plane splitting rules.

Trace Width and Current Capacity

Trace width is set by two different constraints that are often confused. The first is current capacity: a trace of a given copper weight can carry a given current before its temperature rise exceeds the allowance, commonly ten degrees Celsius for an internal layer and twenty for an external one. The second is impedance: if the net must present a defined characteristic impedance, the width is fixed by the stackup geometry.

Where the two conflict, both sets of numbers have to be satisfied, which may mean wider copper on the power nets and controlled geometry on the signal nets. External traces run cooler than internal ones because they can dissipate into air, so an internal trace carrying the same current needs to be wider. The calculation method is set out in trace width current calculation.

Keeping Traces Short and Direct

Short traces are better than long ones for three reasons: less series inductance, less susceptibility to coupled noise and more margin in the timing budget. Route the critical nets first while the board is empty, then the secondary nets, and leave the non-critical connections for last. Routing in the opposite order is what produces a board with one beautifully tuned bus and a dozen detoured clock lines.

Avoid right angle corners on high frequency nets, since the corner presents a local change in width and therefore a small impedance discontinuity. Two forty-five degree segments are the usual substitute. Also avoid unnecessary layer changes on a single net: every via adds inductance and, on a thick board, a stub that degrades the signal as frequency rises.

Crosstalk and Spacing

Parallel traces couple energy into each other, and the coupling rises as the traces get closer and run parallel for longer. The classic guideline is the three times width rule, which keeps the centre to centre spacing of adjacent traces at least three times the trace width where the dielectric thickness allows it. Increasing the dielectric height between the trace and its reference plane reduces coupling further.

Where the pitch is too tight to apply the rule, separate the aggressor and victim by routing them on different layers, by inserting a ground trace between them, or by reducing the parallel run length. The worst cases are not the long buses but the short, tightly packed fan-outs under a package, which is why that region deserves explicit attention.

<img src="https://www.gopcba.com/wp-content/uploads/2026/08/pcb9.jpg" alt="Differential pair routed with matched length on a PCB” />

Differential Pairs and Length Matching

A differential pair has to be routed as a pair. The two traces must have equal length, constant spacing and symmetrical surroundings along their whole path, because any asymmetry converts part of the differential signal into a common mode component that radiates. Bends should be made with matched geometry so the two traces stay in step through every corner.

Length matching also applies to parallel buses with a timing relationship. Where several nets must arrive within a defined skew, the shorter nets are lengthened with a serpentine pattern rather than the longer nets being shortened. The amplitude and pitch of the serpentine matter, since a tight accordion adds its own coupling and impedance variation, as described in serpentine routing and length matching.

Vias in Dense Routing

Blind and buried vias allow a connection between specific layers without penetrating the whole board, which preserves routing space on the layers below. They are the standard solution where a dense area has to be escaped and the board has enough layers to justify the extra process steps. Their main cost is fabrication complexity rather than any electrical penalty.

Ordinary through holes remain the default because they are cheap and reliable. Their drawback is that each one consumes area on every layer, and a dense cluster of them under a package can carve the reference plane into pieces. Fan out the escape pattern so the plane removal is spread out rather than concentrated in one region.

Verifying the Routing

A design rule check confirms that the routing obeys the fabricator capability, covering minimum width, spacing, annular ring and drill size. Signal integrity analysis confirms that the high speed nets meet their impedance and timing targets, and a power integrity check confirms that the plane and decoupling network hold the supply impedance below the target across the band of interest.

None of those checks replaces a review of the return paths by eye. Trace the return current for every critical net from driver to receiver and confirm that the plane beneath it is continuous and that no split lies under the run. Catching that mistake at schematic review costs minutes, and catching it after fabrication costs a new set of boards.

FAQ

Should I autoroute a design? Autorouting works on dense, non-critical digital boards with loose timing. It does not handle controlled impedance, differential pairs or plane splits well, so manual routing of the critical nets followed by autorouting of the remainder is the practical compromise.

How many vias may a signal pass through? As few as possible. Each via adds roughly the inductance of a short length of trace and, on a thick board, a stub that creates a resonance. A high speed net should normally change layers no more than once or twice.

Is a ground pour on the signal layer useful? It helps if it is stitched to the reference plane at frequent intervals and does not leave isolated islands. A pour that is broken into disconnected slivers by the routing acts as an antenna rather than a shield.