ESD Protection in PCB Layout: Techniques That Work

Electrostatic discharge is one of the few design problems that never announces itself. A board that fails an ESD test is easy to deal with; a board that passes every bench measurement and then resets once a week in the field is not. Most of the damage caused by ESD is latent, and latent damage does not look like damage at all, which is why ESD protection has to be designed into the layout rather than added as a component at the end.

Why Most ESD Damage Is Invisible

An electrostatic discharge delivers a very short pulse at a very high voltage. The energy is small, but the current rise time can be under a nanosecond, so the pulse contains frequency content well into the gigahertz range. Two categories of damage follow. Catastrophic damage destroys the device and is caught by electrical test. Latent damage shifts parameters instead of breaking the part: leakage rises slightly, a junction becomes marginally more fragile, a gate oxide is weakened but still functional. It passes the test line and fails in the customer’s hands.

Because the failure is parametric rather than structural, it produces symptoms that look like software faults. Intermittent resets, corrupted transactions on a slow bus, audio clicks, drifting analogue readings and random key errors are all commonly traced back to a discharge event that happened during handling or in the enclosure. Designing for ESD protection means accepting that the layout, not the bill of materials, decides how the product behaves.

Start With the Ground Structure

The single most effective ESD protection measure is a solid, uninterrupted ground plane. A continuous plane presents a low-impedance path for the discharge current, and it also forms the reference that keeps signal return currents close to their traces. A ground plane reduces the common-mode impedance and the inductive coupling of a signal return path by one to two orders of magnitude compared with a board that relies on a grid of traces.

On a multilayer stack-up, place every signal layer next to a plane, and keep the plane free of long slots. A slot in a plane forces return current to detour around it, which enlarges the loop area and turns the slot into a radiating structure. Where a cut is unavoidable, stitch across it with vias at short intervals so the return path has somewhere to cross.

Two-Layer Boards Need a Grid, Not a Scribble

When the stack-up only allows two layers, replace the absent plane with a woven grid of power and ground traces running in both directions. The connections between the horizontal and vertical members are what make the grid work, so fill the intersections with vias and keep the pitch tight. A grid of roughly 13 mm is a reasonable target, and a grid of 60 mm should be treated as the upper limit rather than the goal.

A ground grid is not as good as a plane, but it converts an unpredictable structure into a predictable one, which is what the rest of the layout needs in order to be reasoned about.

<img src="https://www.gopcba.com/wp-content/uploads/2026/08/types-of-pcb-assembly-techniques.webp" alt="PCB layout with a guard ring and chassis ground around the board edge” />

Keep the Discharge Current Path Short

The discharge current has to travel from the point of entry back to the source. Anything that lengthens that journey increases the voltage developed across the board, and it is that voltage, not the original pulse, that damages components. Keep the entry point, the protection device and the chassis reference within a few millimetres of one another, and connect them with short, wide traces. A rule of thumb that works well is to keep the connection length below three times its width, and to treat five times the width as a hard limit.

An RC filter placed at the connector is the standard second line of defence. The capacitor goes as close to the connector as the mechanical layout allows, and the signal is routed through the capacitor before it reaches the receiver. Filters placed a centimetre away from the entry point provide very little ESD protection because the trace between the connector and the capacitor already radiates the pulse into the rest of the board.

Placement Around the Connector

Group connectors along one edge of the board. This keeps the noisy entry region in a known place, and it prevents a discharge on one connector from crossing the whole board to reach another. Place all layers of chassis ground or a polygon fill under the connectors that face the outside world, and tie those layers together with vias at intervals of roughly 13 mm. A broad reference directly under the entry point gives the transient suppressor somewhere to dump current instead of sending it through the signal ground.

Keep I/O circuitry close to its connector, and keep the protected and unprotected sides of the interface apart. A protected signal routed in parallel with an unprotected one will couple the pulse across the barrier, which defeats the protection entirely.

Guard Rings and the Enclosure Reference

Where the board sits inside a metal enclosure, treat the chassis as the final destination for the discharge. A guard ring around the perimeter of the board collects the pulse before it reaches the circuitry inside. For a multilayer board, make the ring at least 2.5 mm wide on each layer and stitch the layers together with vias every 13 mm. For a two-layer board that will not be shielded, leave the ring free of solder mask so it can act as a discharge point, and introduce a deliberate narrow gap in the ring to prevent it from behaving as one large antenna.

Mounting holes deserve the same care. If a metal standoff connects the board to the chassis, a direct connection and a connection through a zero-ohm resistor give different behaviour, and the choice should be a deliberate one. A wide pad on both faces of a mounting hole, with the plating and the chassis reference connected underneath, provides a reliable low-impedance bond.

Signals That Are Prone to Soft Failures

Not every net is equally exposed. Reset lines, interrupt lines, control signals and edge-triggered inputs are the ones that turn a small disturbance into a visible failure, because a few hundred millivolts of noise on an edge-sensitive input is functionally identical to a real command. Route these signals away from the board edge and away from the I/O area, and filter them close to the device they drive.

Length also matters. A long signal trace behaves like an antenna, so route any signal longer than about 300 mm with a companion ground trace beside it, and swap the relative positions of signal and ground at intervals of a few centimetres to keep the enclosed loop area small.

Bypass Capacitors and Magnetic Beads

Every supply pin needs a high-frequency bypass capacitor placed at the pin, not at the far end of the supply trace. The capacitor closes the loop between the supply and the return path, and the smaller that loop area becomes, the less energy the supply network can radiate or receive. Place a bulk capacitor near each connector as well, so that the connector has a local reservoir before the pulse reaches the rest of the board.

Series resistors and magnetic beads are useful in front of a receiver, and sometimes at the driver end of a cable interface. Beads need particular attention during layout: some parts are conductive enough that a signal trace passing underneath one can form an unintended path, which is exactly the kind of error that only appears after the boards come back.

Reviewing the Layout Before Release

ESD protection is decided by a handful of structural choices, so it responds well to a checklist review rather than to simulation. Confirm that the plane is continuous, that the entry region has a solid reference underneath it, that filters sit within a few millimetres of the connectors, that reset and interrupt nets stay away from the edge, and that mounting holes have a defined relationship to chassis ground. Our EMI immunity design notes cover the coupling mechanisms behind these rules, and the layer assignment guidance explains how to choose a stack-up that gives every signal a return path. Both are worth reading alongside the checks in our design release checklist, and the component tolerance and reliability material explains why a marginal part is the one that fails after a discharge.

FAQ

Does a ground plane replace ESD protection components? No. A plane lowers the impedance the discharge sees and keeps currents local, which reduces the damage a pulse can do, but a connector that faces the outside world still needs a transient suppressor and a filter. The plane makes the suppressor effective by giving it a short path to the reference. Without a solid reference the same suppressor can perform very poorly, and the designer will blame the component instead of the routing.

How close does an ESD filter capacitor have to be to the connector? Close enough that the trace between the two is short and wide, ideally below three times the trace width. In practice this means within a few millimetres, and it is worth moving a mechanical part or rotating a component to achieve it. If the capacitor has to be further away, the section of signal trace before it should be treated as an exposed conductor and routed away from sensitive circuitry.

At gopcb, when is ESD protection reviewed? We review it at the layout stage, before the release checklist is signed, because the structural decisions that determine ESD protection cannot be corrected after fabrication. Customers who send us a stack-up and a placement drawing early get the most value from the review, since the entry region, the plane continuity and the connector grouping are all still open questions at that point.