Multilayer PCB Routing Rules and Interface Guidelines

Dense boards are routed on several layers because a single layer cannot carry the connections, but the extra layers introduce their own problems. Two conductors on adjacent layers are separated only by a thin dielectric, so they behave as the plates of a capacitor. Two conductors on the same layer couple through the fringing field. The multilayer PCB routing rules below are the ones that keep those couplings small and the board testable.

Rules That Apply to Every Layer

Route each connection in sequence through the points it has to reach, rather than branching in several directions, so that the path is easy to follow and easy to test, and keep it as short as the placement allows. Where a connection runs between two integrated circuits, the space between and around their pins should be reserved rather than used for other nets, because that area is where escape routing has to happen later.

Keep the routing straight where possible, and where a turn is needed, use a 45 degree chamfer or an arc rather than a right angle. The reason is not only electrical: an included angle greater than 135 degrees also etches more consistently, so the same choice improves both the signal behavior and the manufacturing result. Arrange the traces evenly, and connect the copper pours into one continuous ground area rather than leaving them as isolated islands, since a larger connected ground plane lowers the impedance of every return path.

Placement and Mechanical Coordination

Placement is part of routing. Components should be distributed evenly enough that assembly, insertion, and soldering can be performed without obstruction, and the legend should be placed on the correct silkscreen layer, in a readable orientation, and clear of any pad. Polarized surface mount parts should be marked in the footprint and on the legend so that orientation is unambiguous at the machine and at manual rework.

Functional blocks belong together, so that a circuit and its support components sit as one region rather than being scattered across the board. There is a mechanical constraint on that too: components placed near a display, and particularly near an elastomeric connector, have to keep enough clearance that the connector can be assembled without touching them. Where the placement and the enclosure interact, the mechanical drawing governs.

The last step before release is a continuity review. Every connection should be checked individually, by highlighting each net in turn rather than by trusting the connectivity report, because a net that is nominally connected through a plane can still be isolated by an unintended clearance.

Controlling Crosstalk Between Nets

Coupling between two nets on the same layer can be reduced with three tools. The first is a ground trace or a ground area placed between them, which terminates the fringing field before it reaches the victim. The second is distance, since coupling falls as the spacing grows. The third is parallel length, because coupling accumulates along the run rather than appearing all at once, so shortening the parallel portion by a few millimetres often achieves more than doubling the gap.

Where two nets cannot avoid running in parallel, a large ground area placed on the opposite side of the parallel signals reduces the interference substantially, because the field is shared with the plane instead of travelling between the two traces. A clock is the net most worth protecting in this way: it should run perpendicular to critical signals rather than parallel to them, and its own length should be the shortest the placement allows. The formal statement of the spacing rule is explained in crosstalk and the 3W rule.

Interface-Specific Rules

Standards-based interfaces come with their own geometry, and following them is usually faster than deriving the numbers. An HDMI link is routed as a differential pair with a nominal trace width of 10 mil and a gap of 6 mil, and the spacing between two HDMI pairs is kept above 20 mil so that the pairs do not couple to each other. An LVDS link is also differential, with a narrower trace, around 7 mil wide with a 6 mil gap, chosen to produce a differential impedance near 100 ohms with a tolerance of about 15 percent.

Memory interfaces are where length becomes the governing constraint. For DDR, signals should avoid layer changes, traces should be equal in width and spacing, and the routing should satisfy the 2W rule, meaning that the center-to-center spacing is at least twice the trace width. From DDR2 onward, the fast data lanes also have to be matched in length so that they arrive together, which is impedance control and timing control applied to the same set of nets. The pattern used to absorb the differences is described in serpentine routing and length matching.

Escape Routing and Layer Changes

A dense board spends most of its routing effort escaping from the packages rather than crossing the board. The area immediately around a fine-pitch device is where channels are scarcest, so the escape pattern has to be planned before the rest of the routing claims the space. Charging straight out to the nearest available channel works on a coarse package and fails on a fine one, where the available channels are already committed by the time the escape is attempted. The conventions for fanout are described in escape routing and fanout rules.

Layer changes deserve the same discipline. Each via in a high-speed net adds capacitance and, where the barrel continues past the layer, a resonant stub, so the number of transitions should be minimized deliberately rather than accepted as the router default. Where a transition is necessary, placing it away from a connector and away from the reference plane edge reduces how much it disturbs the local impedance.

Reviewing the Routing

A final review should cover the same ground as the rules above. Confirm that no two adjacent layers carry parallel traces in the same direction. Confirm that the ground pours are connected into one area rather than left as islands. Confirm that critical nets are short, straight where possible, and free of stubs. Confirm that the interface-specific dimensions have been applied to the interfaces that need them. And confirm that every net is actually connected, by highlighting each one in turn rather than by reading the connectivity report.

Ground Planes Are the Real Constraint

Every rule above assumes that the reference plane under a net is unbroken and that the ground pours on the surface are connected to it. Where that assumption fails, the rules stop working. A signal that crosses a split in the plane has no return path beneath it, so the return current takes the long way around, the loop area grows, and the net radiates. The same thing happens when a cluster of vias clears so much copper that the plane becomes a set of islands. Reviewing the plane layers for continuity, and stitching the surface ground to the internal planes with vias at short intervals, is what makes routing rules effective rather than decorative.

FAQ

Why is a right angle worse than a 45 degree bend? Because a sharp corner is a discontinuity that radiates and reflects, and because it etches less consistently than an obtuse angle.

What is the 2W rule for DDR memory? Center-to-center spacing of at least twice the trace width, used to control crosstalk between the parallel data lines.

When should I insert a ground trace between two nets? When the two nets cannot be separated by distance or shortened enough to keep the coupling below budget. The guard must be grounded at both ends and must not form a loop.

Why avoid vias in high-speed nets? Each via adds capacitance and, where the barrel continues past the layer, a resonant stub that removes energy from the signal.