High-Speed PCB Design Challenges: FPGAs, SSN and Routing
It would be convenient if a high-speed PCB design could be laid out as easily as a schematic is drawn, but the two tasks draw on different knowledge. The schematic defines what the circuit does; the layout decides whether it does it at speed. The challenges below are the ones that recur on boards containing a large FPGA or a fast serial link, and each of them has a standard answer that is applied rather than invented.
Where the Challenges Come From
Most boards are the product of two people working from different viewpoints. One understands the devices, their interactions, and the data standards at the interface; the other converts the schematic into copper and may know very little about what the connections are supposed to do electrically. Responsibility for the finished board usually rests with the schematic designer, and that is precisely why the schematic designer benefits from understanding layout: the more the constraints are communicated, the fewer problems survive to the prototype.
The pressure comes from integration. A design with a high-density FPGA is likely to present hundreds of input and output connections, operating frequencies above 500 MHz, and ball pitches as small as half a millimetre. Those three numbers together are what make units interfere with each other in ways that the schematic cannot express.
Simultaneous Switching Noise
The first problem to appear is usually simultaneous switching noise, also called simultaneous switching output. When many outputs change state together, the current they draw from the supply and return networks produces ground bounce and supply noise that affects the whole device, while the high-speed data lines themselves show ringing and coupling. The effect is not a property of any one signal; it is a property of many signals switching at the same instant, which is why it appears on wide buses and not on isolated connections.
Converting the wide bus to differential signaling is the most effective first step. In a differential pair, one conductor sinks the current that the other sources, so the net current stays local and the induced current in the return path is largely eliminated. The same property makes the pair resistant to common-mode interference. At the frequencies involved, up to several hundred megahertz and beyond, the theory is the same as for any transmission line: maximum power transfers when the impedances match, and a poor match produces a reflection that bounces between the driver and the receiver.
Differential Pairs and Controlled Impedance
Differential routing rests on controlled impedance, and the model resembles a coaxial cable: the reference planes act as the shield, the laminate is the dielectric, and the two traces are the centre conductor. FR-4 sits at a dielectric constant of about 4.2 to 4.5, and the uncertainty in that number, combined with the over-etching that production tolerances allow, is what produces impedance error in the finished board. The most accurate way to calculate the impedance is a field solver, which solves Maxwell equations over a cross-section of the actual geometry, taking trace spacing, width, thickness, and dielectric height into account along with the electromagnetic effects they produce.
A differential impedance of 100 ohms has become the industry standard for differential links. It can be built from two 50 ohm single-ended lines of equal length, but because the two traces are close together the coupling between them reduces the differential mode impedance, so the widths have to be reduced slightly to bring the value back to 100 ohms. The result is that each line in the pair has a common-mode impedance slightly above 50 ohms, which is expected rather than a defect. The geometry and the reasoning are developed further in right-angle routing and differential traces.
Microstrip, Stripline and Layer Choice
The geometry also decides how much the pair radiates. In a stripline the signal is buried between laminate on both sides, so all of the field couples to the reference planes above and below and emissions are low. In a microstrip one side of the conductor faces air, whose dielectric constant is the lowest available, which is why the outer layers are the best place for critical signals such as clocks and high-speed serial lanes. A microstrip should still be coupled to a ground plane underneath, because that plane absorbs part of the field and reduces emissions.
Broadside-coupled stripline, where the two traces of a pair sit on different layers, is best avoided. The structure is sensitive to coupling through the reference planes between them, and the impedance is harder to control than a pair routed side by side on one layer. Vias, connectors, and device pads all introduce discontinuities that the geometry alone cannot remove, and where the layout needs more freedom, adding layers or using buried vias is the usual answer, at a cost that has to be part of the plan rather than a surprise. The options are compared in blind and buried via stack selection.
Decoupling and Power Delivery
Every output transition charges and discharges a signal line, and the energy for that has to come from somewhere. The distribution network supplies it in stages. Bulk capacitors handle the low-frequency demand and hold energy for the load steps the regulator cannot follow immediately, and their response extends from DC up to a few hundred kilohertz. Small capacitors with low series inductance supply the fast transients, acting as local energy storage close to the device, and they take over as the bulk capacitors run out of bandwidth.
This is what makes simultaneous switching noise a power delivery problem as well as a signal problem. The large current transients on the supply bus are the same event that couples into the ground network, so adding low-inductance capacitors near the device removes high-frequency energy before it reaches the supply pins. The placement rule is strict: a decoupling capacitor intended to supply a device has to sit within about a centimetre of it, and its routing to the supply and ground pins must be short. Every millimetre of trace, including the vertical distance through the vias, adds inductance and reduces the capacitor effectiveness at exactly the frequency where it is needed.
Clock and Backplane Routing
The clock is usually the most critical net on the board. Routed too long or through a poor path, it amplifies jitter and skew downstream, and the effect grows with frequency. Clock traces should not be spread across multiple layers, and they should contain no vias, because each via adds an impedance change and a reflection at the point where timing matters most. Where an inner layer is unavoidable, the layers immediately above and below should be ground planes to contain the field and reduce delay.
Width becomes a factor as data rates climb. Above roughly 622 MHz the skin effect concentrates current near the surface of the conductor, so a very narrow trace attenuates the signal like a badly designed low-pass filter, with loss rising as frequency increases. On long backplanes the traces should therefore be wider: for runs longer than about 20 inches, widths of 10 to 12 mil are appropriate. When the design uses a PLL inside the FPGA, noise on the supply plane translates directly into jitter, and the usual remedy is a dedicated power island for the PLL, formed by etching a region in the plane so that the analog and digital supplies are separated.
Above 2 Gbps
At the highest rates, the structure of the board itself becomes the limiting factor. Backplane thickness and via design dominate the signal path, and a backplane thinner than about 0.200 inches behaves noticeably better. Keeping the layer count as low as the routing allows limits the number of vias, which matters because in a thick board a via connecting distant signal layers is a long stub, and a long stub is a transmission line branch that distorts the signal. Buried vias solve the problem at a significant cost increase.
The other lever is the material. Low-loss laminates cost close to twice as much as standard FR-4, but above 2 Gbps they are sometimes the only way to reach the receiver with an acceptable eye. The decision belongs with the stack, not with the first prototype failure, because the material changes the impedance geometry as well as the loss.
I/O Isolation and Reference Designs
Not every improvement costs money. Where the pinout allows, reserving the pins adjacent to a high-speed serial lane rather than using them isolates the lane from neighbouring signals. In practice this means leaving a small block of ball positions unused around the transmit and receive pairs, or reserving a whole I/O group near the serialiser. If the design has spare I/O, the technique is free and effective.
The final resource is the device vendor reference design. Manufacturers publish or provide the source layout for the boards they use to characterise their parts, and those layouts contain working high-speed interface implementations that can serve as a starting point. They are usually designed for multiple purposes rather than for one specific product, so they should be adapted rather than copied, but they are far better than beginning from an empty stack.
Underlying all of this is a planning point. Once the layout is finished, changing anything costs time and money, even something as small as a trace width. The constraints have to be established before the effort is invested, and the schematic designer has to stay involved in the choices, because a layout cannot be relied on to infer them. Related spacing and coupling rules are covered in crosstalk and the 3W rule.
FAQ
Why convert a wide bus to differential signaling? Because the two conductors carry equal and opposite currents, so the net current stays local, the return-path disturbance is largely cancelled, and the pair resists common-mode interference.
Why must a decoupling capacitor be so close to the device? Because the trace and the via add inductance in series with the capacitor. Even a small amount raises the impedance at high frequency and defeats the purpose.
What is wrong with broadside-coupled stripline? The two traces sit on different layers separated by a reference plane, which makes the coupling sensitive and the impedance harder to control than a pair routed side by side on one layer.
When should a low-loss laminate be considered? When the data rate exceeds roughly 2 Gbps, or when the link is long enough that the attenuation of FR-4 consumes the timing and amplitude margin.
