PCB Design Review Process and Self-Check Items

A design review is the cheapest defect removal tool available. A problem found on a schematic or a layout costs a comment, while the same problem found after fabrication costs a panel, a schedule slip and a customer conversation. The purpose of a formal review is to make that comparison explicit and to apply it before the design leaves engineering.

When a Review Is Needed and Who Runs It

A review can be requested by the designer or by the hardware developer responsible for the product, and its scope is usually defined by an internal specification that lists what must be verified and who signs off. Small projects often do not need a full review board, but they still need the same checks performed by the designer before submission.

The distinction matters because an unreviewed design still has to pass a manufacturability review at the fabricator. Catching an issue in the internal review is faster and more controllable than discovering it when the order is queried, and the fabricator will not know what the circuit is supposed to do, only that something looks unusual.

Checking Fragile Nets and Loop Area

The first substantive check covers the signals that are most easily degraded: high frequency lines, high speed buses, clocks and any other net that is sensitive to its environment. For each, confirm that the loop area is as small as practical, that the route stays away from interference sources, that it carries no unnecessary vias or detours, and that it never crosses a split in its reference plane.

Crossing a plane split is the most damaging of these, because it forces the return current to take a long detour and turns the trace into a radiator. The same review should confirm that the reference plane beneath each sensitive net is continuous and that the return path is the one the designer intended. The underlying principles are covered in EMI suppression design principles.

Components That Must Not Have Routing Beneath Them

Crystals, transformers, optocouplers and power modules are all disrupted by signals passing underneath them. The rule is to avoid routing beneath these parts on any layer, and in the case of the crystal the requirement goes further: the area beneath it should carry a poured ground plane rather than open laminate or signal copper.

The reason is coupling. A crystal sits on high impedance oscillator pins, so any conductor passing under its body injects noise directly into the clock circuit, and it can also detune the resonator by adding stray capacitance. Transformer and power module bodies are similarly sensitive because of the magnetic fields they contain. Reading a layout with this check in mind is quicker than debugging an intermittent oscillator fault later; the layout guidance is described in MCU oscillator PCB design.

Mechanical Features, Fiducials and Silkscreen

Mounting holes and locating features must agree with the mechanical drawing, a check that is trivial in principle and frequently overlooked in practice. Separately, the features added for manufacturing have to be present and correctly placed: locating holes for electrical test, and fiducials for the placement machine, both sized and positioned according to the process requirement.

Silkscreen is the next item. Reference designators should follow a consistent order, normally left to right and top to bottom, and no legend may cover a pad or a solderable feature. The version number belongs on the silkscreen as well, following the project convention, because a board without a visible revision identifier is difficult to control once units exist in several versions. Fiducial requirements are covered under stencil aperture and placement tolerance.

Completion, Copper Islands and Ground Strategy

Routing completion should be reported rather than assumed. The review checks that the layout is one hundred percent complete, that no dangling trace ends remain, and that there are no isolated islands of copper left floating. A floating copper island is not decorative: it couples to whatever passes nearby and can behave as an unintended antenna.

Ground strategy then gets the same treatment. Power and ground splits must be drawn where the design intends, and any single point connection between two ground domains has to be deliberate, documented and physically present. Where the design carries both analogue and digital returns, the review should confirm they are joined at the intended location and nowhere else.

Gerber Output, Tooling and Handover

The final stage concerns the data package. Every layer must have the correct Gerber settings, with annotations and file names that identify their contents unambiguously, and panelised orders need the drill layer annotated so the fabricator knows which drawing defines the tooling. The output is then verified independently, typically in a CAM tool, to confirm that the files were generated as intended rather than merely that the export command completed.

The review is recorded, not just performed. A completed self-check form travels with the design files to the process engineer, who reviews manufacturability, producibility and testability and returns findings for correction. Closing that loop is what makes the process valuable, since the same class of error tends to recur across projects. Process capability questions are discussed in PCB design quality characteristics.

Power Integrity, Decoupling and Testability

Power distribution deserves its own pass. The review should confirm that each rail is wide enough for the current it carries, that the return path is equally robust, and that the decoupling capacitors are placed close enough to the pins they serve to be effective. A capacitor placed at the far end of a long trace provides little benefit to the device it was intended to protect.

Copper weight, via count between planes and thermal relief on connected pads all affect how the board behaves in manufacture as well as in service. A rail that is adequate electrically but starved of copper can still produce excessive temperature rise, and an unsatisfied thermal relief can make a pad difficult to solder.

Testability is the other half of the review. Every net that must be probed needs an accessible point, and those points need clearance from tall components, from the board edge and from each other, so that a bed of nails fixture can actually make contact. Where in-circuit test is planned, the fixture requirements should be obtained from the test engineer before the layout is released, because adding test points afterwards is often impossible without disturbing routing. Confirm too that any test point is not covered by solder mask or plating that would prevent a reliable contact, and that probing it will not short two adjacent features together.

FAQ

Who should request a design review? Either the designer or the hardware developer responsible for the product. On small projects the designer can perform the self-checks alone, provided the checklist is completed and recorded.

Why is routing beneath a crystal a problem? The oscillator pins are high impedance, so a nearby conductor couples noise into the clock circuit. A passing trace also adds stray capacitance and can shift the oscillation frequency.

What is the point of a Gerber verification step? It confirms that the exported files contain the layers and features the layout actually has. An export that completes without error can still contain wrong polarity, wrong layer names or missing data.