High Speed PCB Layout Myths That Lead to Rework

High speed design accumulates folklore faster than almost any other area of hardware engineering, and some of that folklore is expensive. Three beliefs in particular send teams down the wrong path: that only gigahertz signals need care, that a simulation platform removes the need for measurement, and that the transmission line models inside those platforms are exact. Each contains a grain of truth and each, taken literally, leads to rework.

What Makes a Signal High Speed

The useful definition is not about frequency at all. A signal behaves as a transmission line problem when its edge rate is fast compared with the propagation delay of the interconnect. In practice, when the rise time is smaller than roughly four to six times the delay of the route, the connection must be treated as distributed rather than as a simple wire.

That definition has an immediate consequence that designers often miss. A slow clock on a long board can be a high speed problem, and a fast clock on a very short route may not be. The decision belongs to the route, not to the clock rate printed in the data sheet, which is why the same device can need different treatment in two different products.

Myth One: Only Gigahertz Signals Matter

Believing that only gigahertz signals require care leads to boards where a few megahertz interface is routed casually and then behaves badly. A modern logic family with a sub nanosecond edge contains significant spectral energy in the hundreds of megahertz even when it toggles at a few megahertz, and that energy is what couples, reflects and radiates.

The practical rule is to compute the edge rate and the route delay and compare them, rather than to consult the clock frequency. Where the ratio is close, treat the net as critical and give it a continuous reference plane, controlled impedance and a length budget. Where the ratio is large, ordinary layout practice is genuinely sufficient and the effort is better spent elsewhere.

Myth Two: Simulation Replaces Measurement

Simulation is powerful, but its output depends entirely on the models it is given. A behavioural model derived from current and voltage curves taken at one corner of process, voltage and temperature will not predict behaviour at another corner. Selecting the wrong model variant is one of the most common reasons that a simulation shows a comfortable margin while the measured waveform is marginal.

The useful discipline is to correlate the simulator with the bench. Measure a representative net, adjust the model library until the simulation reproduces the measurement, and only then use the simulator to explore changes. Our notes on impedance tolerance make a related point about fabrication variation, which no model captures unless it is deliberately included.

Myth Three: The Transmission Line Model Is Exact

A microstrip or stripline model built from the stackup and the trace geometry is a good approximation, not a precision instrument. It assumes a rectangular conductor with smooth surfaces and a homogeneous dielectric, and real boards are none of those things. The gap between the model and reality is usually small enough to ignore, and occasionally large enough to matter.

Two effects dominate the difference. The first is surface roughness on the copper, which increases loss at high frequency in a way that depends on the treatment the fabricator uses. The second is the variation of dielectric constant with frequency and with resin content, which is why a material data sheet gives a range rather than a single number. Our discussion of PCB dielectric constant explains how that variation propagates into impedance and delay.

Copper Roughness and Loss in Practice

Copper foil is roughened or treated to improve adhesion to the laminate, and that treatment increases the effective path length for current flowing near the surface. As frequency rises, more of the current concentrates near the surface, so the loss penalty from roughness grows with frequency. At a few gigahertz on a long route the effect can consume a meaningful part of the link budget.

Designers cannot remove the effect, but they can account for it. Where a link is marginal, ask the fabricator which foil type and treatment will be used, and check whether a low profile foil is available. The difference between foil types can be larger than the difference between two nominally similar laminates, and it costs nothing to ask.

What to Do Instead

Replace the myths with three habits. Classify each net by edge rate against route delay rather than by clock frequency. Correlate simulation with measurement on at least one representative net before trusting the model. And treat geometry, material and process as a chain in which the weakest link, not the best datasheet number, determines performance.

Those habits also make reviews faster, because they give the team a shared basis for deciding which nets deserve attention. The alternative, applying a high speed PCB layout rule everywhere without thinking, produces boards that are expensive and slow to design without being meaningfully better than a design that concentrated effort where the physics demanded it.

The same habits apply when the design is reviewed by someone else. A reviewer who asks what the edge rate of a net is, and how long the route is, reaches a useful conclusion quickly, while a reviewer working from a list of clock frequencies will miss the nets that actually matter. Writing the classification down for the critical nets turns a private judgement into something the whole team can check and reuse on the next project, and it shortens every subsequent review.

Working With the Fabrication Data

Finally, remember that the model and the finished board are connected by a stackup drawing. If the dielectric heights in the drawing differ from what the fabricator builds, the impedance will differ too, and no amount of simulation will change that. Request the measured stackup and impedance coupon data when the panels are delivered, and compare them with the design intent.

Keeping that loop closed is what turns high speed layout from a set of beliefs into an engineering process. The techniques for routing high frequency traces and data buses assume exactly this feedback, and they work best when the assumptions behind them are checked rather than inherited.

FAQ

Is a 100 MHz clock a high speed signal? It depends on the edge rate and the route length, not on the clock frequency. If the rise time is short compared with the delay of the trace, the clock must be treated as a transmission line problem. On a short route inside a small board the same clock may need no special treatment at all.

Can I trust a simulator without measurement? For ranking options and finding gross problems, yes. For predicting whether a marginal link will pass, no. Model libraries, corner selection and assumptions about the fabricated geometry all introduce error. Correlating one measured net with the model is the cheapest way to establish how much error to expect.

How much does copper roughness really cost? It depends on frequency, on the foil treatment and on the length of the route. At low frequencies it is negligible, while at several gigahertz over a long backplane it can be a significant fraction of the total loss. Ask the fabricator which foil is being used rather than assuming the smoothest option.