Loop Area: High Speed Signal Integrity: What the Layout Decides

The signals that cause the most trouble on a board are rarely the fastest ones. They are the ones with the worst return path, the largest loop area or the least margin, and those properties are decided by the layout rather than by the datasheet.

Start With the Loop Area

Current returns to its source, and the area enclosed by the outgoing and returning paths is the loop that radiates. The inductance of that loop is what produces the noise voltage, and it scales with the area rather than with the length.

Everything else in high speed design follows from keeping the loop area small. A trace with its return directly beneath it has a loop of almost zero area; a trace whose return detours around a slot has a loop the size of the detour.

Return Path Continuity

The return current follows the path of least impedance, which at high frequency is directly beneath the signal. Where the plane beneath is continuous, the path is a mirror image of the trace and the loop is minimal.

Where the plane is interrupted, the current detours. The detour is what turns a well-designed trace into an antenna, and it is the reason a plane should be checked against the routing rather than assumed to be continuous. Our mixed signal notes describe the check.

Reference Changes and Stitching

Where a signal changes layers, its reference plane changes unless the two layers share a plane. The return current has to follow, and it does so through the nearest available path, which is a stitching via or a decoupling capacitor between the two planes.

Placing a stitching via beside every layer-changing signal via is the standard remedy. Without it, the return finds its own way, and the path it finds is longer and more variable than the one intended.

Edge Rates and the Spectrum

The bandwidth of a digital signal is set by its edge rate rather than by its clock frequency, and a fast edge contains energy well above the clock. That is why a slow clock with a fast driver can produce the same emissions as a fast bus.

The practical response is to slow the edges where the timing allows. A series resistor or a controlled slew rate reduces the high frequency content at the source, which is far cheaper than shielding the result.

Crosstalk and Spacing

Crosstalk is coupling between adjacent traces, and it depends on the length over which they run parallel and on the spacing between them. The coupling falls quickly as the spacing grows, and it rises with the length of the parallel run.

The design levers are therefore spacing and length rather than anything else. Where neither can be adjusted, a ground trace between the aggressor and the victim reduces the coupling, provided it is stitched to the plane at short intervals.

Differential Pairs and Their Discipline

A differential pair carries two complementary signals, and its benefit comes from the tight coupling between them. That coupling requires the two traces to be routed together with a constant separation and a constant length.

A pair that is split to pass an obstacle, or whose two halves differ in length by more than a fraction of the rise time, loses the benefit. The skew converts part of the differential signal into a common mode current, which is the part that radiates.

Impedance Discontinuities

Every change in the geometry changes the impedance, and every change in the impedance produces a reflection. A connector, a via, a stub or a change in width are all discontinuities, and their combined effect is what limits the usable bandwidth of a channel.

The discontinuities cannot all be removed, so they are made small and placed where their effect is least harmful. Keeping a via close to the end of a route, or a connector at the boundary between the board and the cable, is part of that placement.

Verifying the Layout Before the Build

The verification is largely mechanical: overlay the routing on the plane artwork, check the return path of every fast net, confirm that the stitching vias exist beside the layer changes, and measure the length of every differential pair.

The measurements are what make the review objective. A pair whose halves differ by a defined tolerance is either acceptable or not, and the decision does not depend on opinion. Our high speed design notes describe the rules.

Process Control and Verification

On a design of this kind, stitching via is the item that decides how the rest of the board is arranged. Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance. A stack-up that is drawn rather than described removes most of the ambiguity from a quotation, and it lets the fabricator price the board against the dielectric and copper weights that will actually be used.

Where the requirement is not written down, the shop supplies its own default, and the default is chosen for the process rather than for the design. The measurements that matter are the repeatable ones: conductor width and spacing, annular ring, finished hole size, plating thickness and surface finish are all verifiable on a coupon that travels with the panel.

Running a first article through the same checks as the production panel confirms that the two agree, and that comparison is the cheapest form of process control available at prototype stage.

Related reading: our fabrication notes, board quality and design release notes cover the same ground.

Process Control and Verification

On a design of this kind, stitching via is the item that decides how the rest of the board is arranged. Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance. A stack-up that is drawn rather than described removes most of the ambiguity from a quotation, and it lets the fabricator price the board against the dielectric and copper weights that will actually be used.

Process Control and Verification

On a design of this kind, stitching via is the item that decides how the rest of the board is arranged. Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance. A stack-up that is drawn rather than described removes most of the ambiguity from a quotation, and it lets the fabricator price the board against the dielectric and copper weights that will actually be used.

FAQ

Is a four-layer board enough for high speed? It is enough when the signals can be referenced to a continuous plane and the routing is arranged so that the reference does not change. The limit is reached when the congestion forces the return paths to detour, which is a routing problem rather than a stack problem.

How much skew can a differential pair tolerate? A fraction of the rise time of the driver, expressed as a length difference in the material. The figure comes from the driver and the timing budget rather than from a general rule, and it should be stated in the design constraints.

What does gopcb provide for high speed designs? We provide the stack-up with the dielectric properties at the frequency of interest, the impedance calculation for each line geometry, test coupons that carry the same geometry and a coupon measurement with the shipment.