PCB Via Design Optimization and Corner Crack Prevention for Thermal Shock

Thermal shock is one of the key failure causes faced by high-reliability PCB during service. Especially in application scenarios such as aerospace, new energy vehicle electronic control systems, and 5G base station RF modules, PCB must frequently withstand transient temperature cycling from minus 55 to plus 125 degrees Celsius or even wider ranges. Under such working conditions, the coefficient of thermal expansion mismatch between different materials causes significant periodic shear stress, concentrated in the geometric weak areas of the via structure. Among them, the right-angle corner area at the junction between the PTH, or plated through-hole, wall and the inner layer copper ring, namely the corner, is the most sensitive. Microcracks are easily initiated here and accumulate with thermal cycles to expand into penetrating hole wall fracture, or corner crack, ultimately leading to electrical open circuits or increased CAF, or conductive anodic filamentation, risk.

Distribution Characteristics of Thermal Stress in Via Structures

A via is not an ideal homogeneous body. It is composed of FR-4 or high-frequency materials such as Rogers RO4350B, hole wall electroplated copper with thickness usually 18 to 25 micrometers, inner and outer layer copper foil of 12 to 35 micrometers, and possibly nickel and gold surface treatment layers. The CTE differences among components are significant. The Z-axis CTE of FR-4 is about 60 to 70 ppm per degree Celsius for unmodified substrate, while copper is only 17 ppm per degree Celsius. When undergoing rapid temperature rise and fall with typical thermal shock rates of 10 degrees Celsius per second or more, the board expands and contracts sharply along the Z axis, but the copper layer is constrained in-plane, generating reverse tensile or compressive strain. This strain converts into shear stress at the interface between the hole wall copper layer and the dielectric and forms a stress concentration factor, or SCF, as high as 2.8 to 3.5 at the 90 degree inner corner where the inner layer pad meets the hole wall, as verified by finite element simulation based on ANSYS Mechanical 2023 R2 with boundary conditions of delta T equals 180 degrees Celsius and heating rate of 15 degrees Celsius per second. The actual stress level in this area can exceed the yield strength of electroplated copper at about 250 MPa, inducing local plastic deformation and microvoid aggregation.

Microscopic Morphology and Failure Mechanism of Hole Wall Fracture

Scanning electron microscopy, or SEM, fracture analysis of failed samples shows that corner crack has typical brittle-ductile mixed fracture characteristics. The initiation point is always located near the vertical intersection line between the outer edge of the inner layer copper ring and the hole wall copper column. The initial crack propagation direction is parallel to the Z axis, then deflects into the board thickness direction in the X and Y plane, forming a stepped path. Energy dispersive spectroscopy, or EDS, confirms that there is no obvious copper oxide enrichment in the crack path, ruling out a purely electrochemical corrosion dominated mechanism. Electron backscatter diffraction, or EBSD, shows high-density dislocation pile-up and grain orientation mutation at the crack tip, confirming that thermomechanical fatigue is the main cause. It is worth noting that when the inner layer copper ring size is less than 1.8 times the hole diameter, for example a 0.3 mm hole with a 0.5 mm ring, stress redistribution intensifies, and the probability of crack occurrence increases by 400 percent according to IPC-9708 accelerated thermal shock test data after 500 cycles.

Key Design Parameter Optimization Strategy

Preventing corner crack requires collaborative optimization from three dimensions: geometric configuration, material matching, and process control. First, eliminating the 90 degree right-angle transition is a fundamental measure. It is mandatory to require the inner layer copper ring to use a teardrop shape or filleted pad, so that the edge curvature radius is 0.15 mm or more. Measurements show that this design can reduce the stress concentration factor to below 1.4. Second, strictly control the annular ring ratio, or ARR. For conventional 1.6 mm thick FR-4 boards, ARR of 2.2 or more is recommended, that is, ring width of 1.2 times the hole diameter or more, and zero ring width designs such as HDI microvias directly connected to BGA solder balls should be avoided. Third, for high CTE boards, the hole wall copper thickness must be increased to 25 micrometers or more, compared with the IPC-6012 Class 2 requirement of 20 micrometers, and pulse plating process should be used to improve copper layer ductility with elongation of 12 percent or more, better than the 8 percent of DC copper plating.

Material Selection and Stack-Up Matching Points

Substrate selection directly affects the thermal stress amplitude. Under the premise of meeting dielectric performance, priority should be given to low expansion boards with modified Z-axis CTE, such as Isola IS410 with Z-CTE of 50 ppm per degree Celsius or less, or Panasonic Megtron 6 with Z-CTE of about 45 ppm per degree Celsius, reducing thermal mismatch by 30 percent compared with standard FR-4. At the same time, stack-up design must avoid hard-soft-hard alternating structures. For example, inserting low modulus PP between high Tg boards will cause stress reflection and superposition at the interface. A full stack-up CTE gradient matching scheme is recommended. From the surface layer to the core board, Z-CTE decreases successively, such as outer layer PP at 65, core board at 55, and inner layer PP at 48 ppm per degree Celsius, so that thermal strain transitions smoothly along the thickness direction. After a certain automotive ADAS controller PCB adopted this scheme, its life in minus 40 to plus 125 degrees Celsius thermal shock testing increased to 2,200 cycles under IPC-9708 Level 3 standard.

Process Control and Manufacturability Verification

Design optimization must be implemented through process assurance. In the drilling stage, small diameter cemented carbide drill bits should be used, with micrometer-level edge precision drill bits selected when diameter is 0.25 mm or less, and feed rate should be strictly controlled at 1.5 m per minute or less and retraction speed at 3 m per minute or more, avoiding microcracks or burrs on the hole wall. Such initial defects can easily become crack sources under thermal shock. The desmear process before copper deposition is particularly critical. Using an improved alkaline potassium permanganate system rather than the traditional sulfuric acid-chromic acid system can reduce the bell mouth effect on the hole wall caused by excessive etching of epoxy resin and ensure uniform coverage of electroplated copper on the hole bottom. Final verification must perform dual-mode accelerated testing. First, 1,000 thermal shocks per JEDEC JESD22-A104 standard at minus 65 to 150 degrees Celsius with 15 minute dwell, then superimpose 1,000 hours of high temperature and high humidity bias testing per IPC-TM-650 2.6.27.1 at 85 degrees Celsius and 85 percent RH with 100 V DC, comprehensively evaluating the coupled failure risk of corner crack and CAF. Qualified products must meet: all via resistance change rate less than 5 percent, and X-ray inspection with 2D X-ray at resolution of 5 micrometers or less confirms no sign of hole wall separation.

Engineering Practice of Advanced Structure Design

For extreme thermal environments, the industry has developed two types of enhanced via structures. The first is a buried via and blind via composite structure, or stacked microvia with filled via-in-pad. In BGA areas, 0.075 mm laser blind vias filled with conductive silver paste are used, and 0.15 mm mechanical buried vias with fully filled electroplated copper are stacked on top, completely avoiding PTH through stress. Measured thermal shock life reaches 3,500 cycles. The second is a stress relief slot design. A 0.05 mm wide annular slot is etched 0.3 mm around critical signal vias, with depth equal to the dielectric layer thickness, and the slot is filled with low modulus silicone adhesive with elastic modulus of 1 MPa or less, so that local thermal strain is absorbed by slot deformation. After a certain satellite payload PCB applied this technology, the corner crack occurrence rate in minus 196 degrees Celsius liquid nitrogen quenching tests was zero, with 1,200 vias and 100 cycles. It should be emphasized that such designs must be combined with DFM tools for thermal-mechanical coupling simulation and clearly mark slot positions and filling requirements in the Gerber output to avoid PCB manufacturers misjudging them as defects.