Power Sequencing and Rail Tracking Design

A board with several supply rails is not powered up by connecting a supply to it. Each rail has to reach its nominal value in the right order and within a defined time, or the devices that span two rails can be damaged, latch up, or draw current through paths that were never designed to carry it. power sequencing is the discipline that prevents that, and it is mostly implemented in the layout and the passive network.

Why Sequencing Matters

A device with two supplies often contains internal structures that connect them. If one rail is present and the other is not, current can flow through those structures from the powered rail to the unpowered one, and the resulting current is limited only by the impedance of the path. On a processor with a core rail and an interface rail, that can mean an input pin at a higher potential than its own supply, which is a condition the datasheet forbids.

Sequencing also prevents unpredictable logic states. A controller that boots while its memory is unpowered may drive an output that the memory is not ready to accept, and a converter that starts before its reference is stable may produce an output that overshoots. Both effects are avoided by a defined order.

The requirement comes from the device datasheets, and it is best collected on a single page during the design rather than discovered during bring-up. Each device that has more than one supply has a recommended sequence, a maximum time between rails, and usually a condition on the reset signal relative to the supplies.

Sequencing Order and Timing

A typical order brings up the core rail first for processors that require it, then the interface rails, then the analogue supplies, with the reset released last. Some devices require the opposite order at power down, which means the sequencing circuit has to act on both edges rather than only on the ramp up.

The time between rails is usually specified as a maximum, and often as a minimum as well. A few milliseconds is typical, and the requirement is satisfied by a chain of enable signals with their own delays rather than by hoping that the converters start at different times because of their soft start settings.

The reset signal is the last element and the easiest to get wrong. A reset that is released before a rail is in regulation leaves the device in an undefined state, and a reset that is released too late wastes power up time. The reset should be driven from the power good signals rather than from a fixed delay, so that the sequence adapts to the actual ramp rate.

Rail Tracking and Coincident Supplies

rail tracking holds two rails at the same potential throughout the ramp so that the difference between them never exceeds a limit. Coincident tracking keeps the voltages equal, while ratiometric tracking keeps them proportional to their final values. Both are used where devices, such as field programmable gate arrays and some processors, specify a maximum difference between core and interface supplies.

Tracking is achieved either by a dedicated controller with a shared ramp or by connecting the feedback networks so that the error amplifiers see the same reference. The second method is simpler but requires that both converters have compatible feedback arrangements and that their compensation suits the shared behaviour.

Where tracking is not possible, the difference between rails has to be limited by the sequence alone. A device rated for a maximum of three hundred millivolts between two rails, for example, requires that the second rail comes up within a short time of the first. Checking that limit against the measured ramp is part of the power up verification.

Enable Thresholds and Power Good Signals

An enable threshold is the voltage at which a converter begins to operate, and it is not a precise number. The datasheet gives a range, and the actual value depends on temperature and on the part. A sequencing chain that relies on one converter enabling the next must account for the full range, or the margin between steps will vanish at the extremes.

A power good signal is an output from the converter that indicates the output is within regulation, and it may be an open drain output that needs a pull up. Using it to release the next enable gives a chain that follows the real behaviour of the supplies, while using a fixed delay gives a chain that follows an assumption.

Pull up resistors on power good signals should return to a rail that is present early in the sequence, otherwise the signal cannot be read until the last rail is up. This is a common design oversight that produces a board which works until the sequence is analysed in detail, and the fix is a single resistor connected to the right rail.

Inrush Current and Slew Rate Control

inrush current is the surge that flows while the input capacitors of a converter charge. On a board with several large capacitors and a low impedance supply, that surge can reach tens of amperes for a few hundred microseconds, enough to trip a fuse, to dip the supply below the reset threshold of another device, or to weld a connector contact over time.

Soft start controls the ramp of the output and, indirectly, the input current. A controller with an adjustable soft start lets the designer stretch the ramp so that the input current stays within what the supply can deliver. The trade is a longer power up time, which matters in equipment that has to be ready quickly after switch on.

A series element at the input, such as a resistor with a bypass switch or an active current limit, controls the surge directly. The bypass switch then carries the operating current and the resistor is shorted out, so the loss is only present during the start. The traces and the connector have to carry the surge, and the width needed for a given current is covered in our guide to trace width and current.

Layout of the Sequencing Network

Keep the sequencing components near the converter they control, and route the enable and power good signals as short, direct connections rather than across the whole board. A long enable trace can pick up noise and enable a converter during an unrelated transient, which produces a partial power up that is difficult to reproduce.

Place the pull up resistors where they are easy to probe, and label the nets so that the sequence can be followed on the schematic. Where several rails are sequenced, a small test point on each enable and each power good net makes verification a matter of minutes instead of hours, an approach that pays off in production as well as in development.

The input capacitors of the converters should be placed close to the input pins, with their returns to a common point rather than distributed along a plane. The path that the inrush surge takes is the same path that the switching current takes, so the loop rules in our guide to converter layout and routing apply to the start up event as well as to normal operation.

Verification and Common Faults

Verify the sequence with a scope that can record several channels at once. Trigger on the first rail rising and record every rail, the enable signals, the power good signals and the reset line. The recording shows both the order and the timing, and it can be compared directly with the requirement.

A board that works at room temperature but fails at the temperature extremes usually has a marginal enable threshold. The threshold of a converter moves with temperature, so a chain that relies on a narrow margin will occasionally reorder itself. Increasing the delay between steps or using power good signalling removes the dependence on the threshold.

A device that draws excessive current at power up but works normally afterwards points to a sequencing violation, where current flows through an internal path during the ramp. Checking the difference between the rails during the first few milliseconds identifies it, and the fix is in the sequence rather than in the device. Manufacturing notes for the test points and the fixture access needed to make those measurements are collected in manufacturable PCB design.

FAQ

What happens if I power up the rails in the wrong order? Often nothing visible, which is the danger. The damage may appear as increased leakage, a reduced lifetime or a latch up that occurs only under one combination of temperature and supply rate.

Do I need a dedicated sequencing chip? For two rails, a couple of resistor capacitor delays and the power good outputs are usually enough. Above four rails, a dedicated device is easier to verify and to modify.

How long should the delay between rails be? Long enough that the first rail is in regulation with margin under all conditions, and short enough to satisfy any maximum time in the device datasheet. A few milliseconds is a common starting point.