Differential Via: Key Checks Before Release

A differential pair that runs cleanly on one layer and then changes layer through a via is no longer a differential pair at that point. The transition introduces an impedance discontinuity, an opportunity for the two halves of the pair to become slightly different, and a return path question that the designer has to answer. At low speeds none of this matters, and at the speeds where differential signalling is chosen in the first place, the transition is often the weakest part of the channel.

What a Via Does to a Pair

A via is a short vertical transmission line with its own characteristic impedance, its own propagation delay and its own capacitance to any plane it passes through. The capacitance of an unused pad or an anti-pad that is too large creates a local drop in impedance, which reflects part of the incident wave. Where the pair passes through several planes, the effect accumulates.

A differential pair has two such transitions, and if they are not geometrically identical the pair becomes slightly unbalanced. The imbalance converts part of the differential signal into a common mode component, which radiates and which the receiver rejects less well than the differential signal it is designed to detect. This conversion, sometimes called mode conversion, is one of the reasons a pair can pass a single ended test and still fail in a system.

The transition also changes the effective length of the two traces if the vias are placed so that one is slightly longer or if the layer change is asymmetric. The result is skew between the two halves, which reduces the differential amplitude and adds its own common mode component.

Impedance Discontinuity

The impedance discontinuity at a via is caused by its capacitance, which is proportional to the area of the pads and the anti-pads and inversely related to the distance to the reference planes. Reducing the pad size to the minimum the design rules allow, keeping the anti-pad close and removing unused pads on the layers that the via does not connect to all reduce the capacitance and therefore the discontinuity.

Removing the unused pads is one of the most effective single measures, and it is often omitted because the design rules do not require it. A short stub from an unused pad, or a long non functional pad on an inner layer, adds capacitance without any benefit. Where the stackup allows, a back-drilled or stub-free via structure removes a further contribution at high speeds.

The effect can be estimated before layout. A first order calculation of the via capacitance and inductance gives the approximate impedance of the transition and its electrical length, which is enough to decide whether the discontinuity is tolerable or whether the via needs to be tuned. The estimate does not need to be exact because the comparison is between the via and the rest of the channel.

Return Path Continuity

The return current for a differential pair flows in the reference plane beneath it, and the pair’s own two currents largely cancel in the plane when the pair is balanced. At a via transition, the return current has to move to the new reference plane, and it can only do so through a path that the design provides. Stitching vias between the two reference planes, placed close to the signal vias, provide that path.

The placement of the stitching vias matters as much as their presence. A ground via placed several millimetres away forces the return current into a long detour, which increases the loop area, adds inductance to the transition and increases both the reflection and the emissions. Placing the ground vias symmetrically around the signal pair, at the smallest distance the design rules permit, is the standard practice.

Where the reference planes are at different potentials, a capacitor can provide the return path at high frequency, but it must be placed as close to the transition as the ground via would be. A capacitor placed on the far side of the board is electrically somewhere else entirely and provides no useful path at the frequencies involved.

Geometry of the Via Pair

The two vias of a differential pair should be treated as a pair in the same way as the traces. The spacing between them should be maintained through the transition so that the differential impedance does not change abruptly, and the two vias should be identical in pad size, anti-pad and drill. Any asymmetry converts differential signal into common mode.

The entry and exit of the traces into the vias should be handled in the same way as a pad connection, with the two traces arriving at the same angle and with the same length. Where a trace has to fan out to reach the via, the additional length should be given to both halves equally, and the fan out should be symmetrical about the centre line of the pair.

Ground vias placed on both sides of the pair, and sometimes between them at a greater depth, form a structure that carries the return current and also constrains the field. The arrangement should be symmetrical, because an asymmetric ground structure reintroduces the imbalance that the rest of the design has been trying to avoid.

When to Worry

Not every via needs attention from a signal integrity point of view. The discontinuity matters when its electrical length is a significant fraction of the rise time, and for a short via in a thick board the effect may be negligible at moderate speeds. The budget approach applies: estimate the contribution and compare it with the margin available in the channel.

Where a channel has several transitions, the effects add and the individual contributions have to be smaller. A backplane with four layer changes is a different problem from a daughter card with one. This is a case where counting the transitions during layout planning is more useful than analysing any single one of them.

The frequency content of the signal decides as well. A pair carrying a signal with a fast edge and a low repetition rate is just as demanding as a fast clock, because the edge content is what the interconnect has to pass. Judging the requirement from the data rate alone is a common and expensive mistake.

Design Practice

The practical measures are consistent: minimise pad and anti-pad size, remove unused pads, keep the two vias identical and closely spaced, place ground stitching vias symmetrically and close, and keep the reference planes continuous through the transition. None of these is difficult, and all of them require attention during layout rather than afterwards.

Where the design permits, transitions should be avoided altogether. Routing a critical pair on a single layer from driver to receiver removes the problem entirely, and it is worth spending layout effort to achieve it. Where a transition is unavoidable, the measures above reduce its contribution to a level that the channel budget can absorb.

The layout should be reviewed against these rules before release, and the review should look at every transition on the critical pairs rather than at a sample. A single neglected transition can consume the entire budget for a channel, and it will not be visible in the schematic or in the netlist.

Practical Rules

Treat the via pair as a pair: identical geometry, constant spacing, symmetric fan out and symmetric ground stitching. Minimise the capacitance of the transition by reducing pads and removing what is unused.

Count the transitions on every critical channel and compare the total contribution against the margin available. Verify with a coupon or a measurement where the design justifies it, and record the results with the fab and test records so that the quality data can be checked against the process that produced the board.

FAQ

Why is a via a problem for a differential pair? Because it introduces an impedance discontinuity and, if the two halves are not identical, converts part of the differential signal into common mode.

What are stitching vias for? They provide a path for the return current between reference planes at the transition. Placement close to the signal vias is what makes them effective.

Should unused via pads be removed? Yes. They add capacitance without benefit, which increases the impedance discontinuity at the transition.