Impedance Controlled Stackup Design

Impedance control means that the characteristic impedance of a trace is specified as a number and built to a tolerance, rather than being accepted as whatever the geometry happens to give. It matters for every interface that has a specification attached, from a single ended clock to a differential pair, and the number that matters at the end is not the one in the design tool but the one a test coupon reports.

Why the Number Matters

A trace carries a signal and an impedance. Where the impedance changes along the path, part of the signal reflects, and the reflection appears as an overshoot, a ringing or a step that a receiver may interpret incorrectly. At low frequencies the effect is invisible; as the rise time shortens, the same geometry that was acceptable becomes a problem.

The requirement usually arrives with the interface specification. A memory bus, a serial link or an antenna feed will state a single ended or differential impedance and a tolerance, and the board is then designed so that the traces on the specified layers fall inside that band.

Everything that is not specified still has an impedance, and it varies with the layer, the width and the surrounding copper. The discipline of impedance control is to know which nets need the specification and to design the stack so that those nets land where the specification requires.

The Stackup Comes First

The stackup is the set of layer thicknesses and dielectric materials, and it determines the geometry that will give a target impedance. A 50 ohm microstrip on a thin dielectric is a narrow trace, while the same impedance on a thick dielectric is a wide one, and the choice between them is a routing decision.

The reference plane is as important as the trace. A microstrip references the plane directly beneath it, while a stripline references two planes, one above and one below. The reference must be continuous along the whole path, because a trace that crosses a split in its reference plane has a return current that has to detour, which changes the impedance locally and creates a radiating loop.

Dielectric thickness tolerances and the dielectric constant of the material both enter the impedance equation, and both vary. The thickness is controlled by the fabricator, and the dielectric constant varies with the resin content, the glass style and the frequency, so the stackup should be designed around the range rather than the nominal value.

Trace Geometry

The width controls the impedance for a given stack, and the copper thickness modifies it because a thicker copper trace is electrically slightly wider. A design that specifies a width without a tolerance on the plating thickness is asking for a variation that the fabricator cannot avoid.

Differential pairs add the spacing between the two traces as a variable. The pair has a differential impedance and also a common impedance, and the two respond differently to width and to spacing. Getting the differential figure right while the common figure drifts is a common outcome of a design that only checks one number.

The environment of the trace also matters. A dense array of vias, a copper pour that comes close to the trace or a neighbouring trace at a similar height all shift the impedance, and the shift is largest where the geometry departs most from the assumption used in the calculation.

Single Ended and Differential

A single ended trace has an impedance referenced to ground, usually 50 ohms, and it is simpler to control because there is one geometry to hold. The return current flows in the plane beneath, and the loop area is small as long as the plane is continuous.

A differential pair is specified by the differential impedance, usually between 85 and 100 ohms, and the two traces should be routed together with a constant spacing. The coupling between them means that the pair behaves partly as a system, and separating the traces anywhere along the path changes the impedance of that section.

Where a pair has to be separated to pass through a via field or around a component, the separation should be kept short and symmetric. A short break in the coupling is tolerable; a long one makes the pair behave as two single ended traces with an impedance that the receiver does not expect.

Fabrication Tolerances

The variables the fabricator controls are the dielectric thickness, the trace width after etching and the plating thickness. Each has a tolerance, and the impedance tolerance is the combination of them, which is why a design that asks for a very tight impedance band also drives the price.

Etching removes copper from the sides as well as the top, so the finished width is narrower than the artwork. The reduction depends on the copper thickness and on the process, and it is one of the reasons why a design transferred from a thin copper layer to a thick one measures differently.

The impedance should be verified on a test coupon that is built on the same panel with the same process. The coupon carries traces of the specified geometry, and the measurement reports the actual impedance, which is what the customer receives. A coupon is worth more than a calculation because it captures every process variation at once.

Design and Verification Flow

The flow starts with the interface specification, moves to a stackup that can deliver it, then to a geometry that the fabricator can hold, and finally to a coupon that proves it. Each step constrains the next, and changing the stackup late invalidates the geometry that was calculated from it.

The layout should carry the impedance requirement on the nets that need it, with the layer and the target recorded. Where a net is routed on a layer that was not part of the calculation, the requirement is not met even if the width is correct.

Verification is a measurement, not a simulation. The coupon result should be compared with the target and the tolerance, and where it falls outside, the response is to adjust the stackup or the geometry rather than to accept the board, because the interface specification is a contract.

Practical Rules

Fix the stackup before the routing, keep the reference plane continuous, and hold the geometry constant along the whole net. Specify the impedance with the layer and the tolerance on the fabrication drawing.

Settle the stackup with the fabrication notes and the laminate data, verify it with the impedance coupon and the high speed rules, and confirm that the microstrip and stripline routing matches the layer that was calculated.

FAQ

Why does the stackup have to be fixed before routing? The geometry that gives the target impedance depends on the dielectric thickness. A late change to the stackup invalidates every width that was calculated from it.

What causes an impedance to drift from the calculation? Dielectric thickness and constant tolerances, etching that narrows the trace, plating thickness and nearby copper. The test coupon captures all of them at once.

Should a differential pair be kept together? Yes. The coupling is part of the impedance. Keeping breaks short and symmetric limits the effect of the sections where the pair is separated.