Controlled Impedance: Preparation, Placement and Process Control

Controlled impedance turns a geometric feature into an electrical specification. A trace of a given width, on a given layer, above a given reference plane has a characteristic impedance, and the design says that impedance must stay within a tolerance. Making that true requires the stackup, the artwork compensation and the fabrication process to agree, and verifying it requires a coupon and a measurement. This article covers the chain from the design calculation to the measurement that confirms it.

What Controlled Impedance Means

A trace has a characteristic impedance determined by its geometry and by the dielectric around it. When the signal rise time is short relative to the trace length, that impedance controls how the signal propagates and how much of it reflects at a discontinuity. Controlling impedance means holding that value within a band across the whole board and the whole production run.

The requirement is usually expressed as a target with a tolerance, such as a differential pair at a specified value within ten percent, and it applies to a defined reference condition that should be stated with the target. The tolerance covers the design, the fabrication and the measurement, so it has to be divided among them rather than applied only to the finished trace.

Stackup and Geometry Calculation

The impedance depends on the trace width, the dielectric thickness, the dielectric constant and the presence of a reference plane. The stackup fixes the dielectric thickness, so the width becomes the design variable. A small change in thickness or in dielectric constant moves the impedance, which is why the stackup must be agreed with the fabricator before the routing is finalised.

The dielectric constant is not a single number. It varies with frequency and with the resin to glass ratio, which changes across a panel and between prepreg and core. The calculation should use the material data for the frequency band of interest and should include a tolerance for the material, not only for the geometry. The material behaviour that drives this is described in PCB laminate material properties.

<img src="https://www.gopcba.com/wp-content/uploads/2025/09/厚铜板.jpg" alt="Impedance test coupon on a PCB panel connected to a time domain reflectometer” />

Coupon Design and Placement

A test coupon is a structure on the panel that can be measured to verify the impedance. It is normally built alongside the boards with the same stackup and the same process, so that the measurement represents the product. The coupon should include the same trace types as the product: single ended, differential pairs, and the same widths on the relevant layers.

The coupon design matters. It needs a launch structure that the measurement probe can contact repeatably, a length long enough to give a clean reading and enough separation from adjacent structures to avoid coupling. Where the board has several impedance requirements, the coupon should cover each of them, and the coupon position on the panel should be recorded so that measurements can be compared over time. The general principles of coupon design are covered in PCB test coupons.

Measurement Method

Time domain reflectometry is the usual method. A fast edge is launched into the coupon and the reflection is analysed to derive the impedance along the trace. The result includes the launch and the probe, so the measurement setup has to be calibrated with a reference structure and the probe has to contact the coupon consistently.

Frequency domain measurement with a network analyser is an alternative that gives the impedance over a frequency band and can also show loss. It needs a calibrated connection and more interpretation, but it captures behaviour that a single time domain reading does not. Whichever method is used, the record should state the instrument, the calibration, the probe and the coupon, because the number is only meaningful with that context. The measurement discipline applied in high speed design rules is the same one used here.

Tolerance Budget and Its Distribution

The measured impedance varies because of trace width tolerance, dielectric thickness tolerance, dielectric constant variation and measurement error. A useful tolerance budget assigns a share to each and confirms that the total is within the specified band. Without that, a board that measures outside the band gives no indication of which contributor to correct.

The budget also shows where money should be spent. Tightening the trace width tolerance is only useful if the thickness tolerance is comparable, and tightening both is pointless if the material variation dominates. The fabricator should provide the tolerance they can hold before the design is released, and the design should be checked against it rather than against an ideal value.

Process Control During Fabrication

Fabrication controls the geometry through imaging, etching and lamination. Etch compensation adjusts the artwork width for the amount of copper the process removes, and it must be verified for each layer and each copper thickness. Lamination controls the dielectric thickness, and the press parameters and the material lot affect the result.

The measurement result feeds back into the compensation. Where a coupon consistently measures high, the compensation is adjusted or the width is increased, and where the variation is large the process is investigated before the design is changed. Keeping the measurement record with the panel lot makes that feedback possible, and it shows whether a change in the result came from the process or from the material.

Design Changes That Move the Impedance

Any change to the stackup or the routing moves the impedance, and the effect should be estimated before the change is made. Adding a layer changes the reference planes and the dielectric thicknesses, changing the copper weight changes the thickness of the plated trace and the finished width, and re routing a trace over a plane split changes the return path and therefore the effective impedance.

Changes that appear cosmetic also matter. A solder mask over a trace changes the effective dielectric constant slightly, and so does a conformal coating. Both are normally included in the calculation as a defined condition, and the measurement should be taken with the same condition applied, otherwise a board that meets the requirement before coating may measure differently afterwards.

Verification and Reporting

Verification should be reported per panel lot with the coupon result, the measurement conditions and the disposition where the result is out of tolerance. A single number for a production run is not informative, because it hides the distribution that determines how many boards are actually within the requirement.

The gopcb fabrication group reports impedance measurements as a distribution against the target band and flags lots that are near the limit rather than only those that exceed it. That early warning allows the process to be corrected before it produces out of tolerance material, and the acceptance criteria for the finished board follow the same class based reasoning as any other electrical requirement.

FAQ

Can impedance be verified on the product board rather than a coupon? It can be measured on a product trace if there is a suitable launch and a reference plane, but the coupon remains the standard method because it is designed for measurement.

How much tolerance is realistic? It depends on the stackup and the material, but a ten percent band is common and a tighter band requires a well controlled dielectric thickness and a stable material.

Does the measurement include the probe? Yes, so the setup must be calibrated and the probe contact must be repeatable. Comparing results from different probes without calibration is not meaningful.