Clock Buffer Design on High Speed PCBs

A clock buffer looks like a trivial part. It takes an input clock and reproduces it on several outputs, which sounds like something a designer should never have to think about twice. In practice the buffer is where the clock tree acquires most of its added jitter, where supply noise enters the timing budget, and where a layout decision made for convenience quietly reduces the margin of every synchronous interface on the board.

What a Clock Buffer Does to a Clock Tree

A clock tree distributes one timing reference to many loads. Each load adds capacitance, and a single driver with a large fanout will have slow edges, a compromised swing and a delay that depends on how many loads happen to be switching. A buffer breaks that dependency by presenting a defined load to the source and driving the branches from a low-impedance output.

The benefit is isolation as much as drive strength. With a buffer in the path, noise on one branch no longer travels back to the oscillator, and the delay from the reference to each branch is defined by the buffer rather than by the sum of every load on the net. That is what makes the clock tree analysable at all.

Fanout and Loading

Fanout is not a count of pins; it is a statement about loading. The relevant question is what the buffer sees at the end of each branch after the trace capacitance, the input capacitance of each device and the parasitic elements of vias and connectors are included. A branch that looks short can still present a heavy capacitive load if it passes through a connector.

The layout consequence is that branch length has to be planned rather than discovered. Our notes on high speed PCB layout floorplanning describe how to allocate space for the clock tree before the rest of the routing fills the board, which is the only point at which the allocation is cheap.

Added Jitter and the Timing Budget

Every stage in the clock path contributes jitter, and the buffer’s contribution has two parts. The first is the intrinsic jitter of the device, which the datasheet specifies and which rises when the input slew rate is slow. The second is jitter converted from supply noise, which depends on the buffer’s supply rejection and on how much noise reaches its supply pins.

Because the two add in a root-sum-square sense along the path, a chain of three buffers contributes more than three times the jitter of one, which is why long clock chains are avoided where the timing budget is tight. If the budget allows one buffer, adding a second for layout convenience is a decision that should be made explicitly and recorded.

Supply Noise and Power Integrity

The conversion of supply noise into timing jitter is the mechanism that catches most teams. A buffer with a clean input and a dirty supply will deliver a clock whose edges move with the supply, and the noise source is often a switching regulator or a fast interface sharing the same rail.

Layout is the main defence. Short, wide connections to a local decoupling network, a reference plane that is continuous under the device, and separation between the clock supply and the noisy rail all reduce the coupling. Our notes on power plane splitting rules explain when separating rails is worth the discontinuity it creates and when it merely moves the problem.

Output Format and Termination Choices

Buffers come with several output formats, and the choice is not only electrical. A low-voltage differential output offers good common-mode rejection and low jitter at the cost of two pins and a termination network per pair, while a single-ended output is simpler and needs care to avoid reflections on a long branch.

Termination also affects the load the buffer sees. A series resistor at the source isolates the trace from the driver, while a parallel termination at the load absorbs the reflection but draws static current. The right answer depends on the branch length relative to the edge rate, and it should be decided together with the branch geometry rather than chosen from a table afterwards.

Layout Rules Around the Buffer

Physically, a clock buffer is a small analogue circuit that deserves analogue treatment. Its decoupling capacitors belong adjacent to its supply pins with a short return to the plane, its differential outputs should be routed as a pair with consistent spacing, and its unused outputs should be terminated rather than left open, because an unterminated output still switches and still radiates.

Reference continuity is equally important. A clock net that crosses a plane split has a return path with an undefined shape, which converts a clean square wave into one with a shelf, and that shelf moves the effective threshold of the receiving device. Our notes on MCU oscillator PCB design cover the same principles at the source end of the clock path.

When Not to Use a Buffer

Buffers are not free, and there are cases where they make the timing worse. A single load placed close to the source is usually best driven directly, and a low-skew requirement may rule out a buffer whose channel-to-channel skew exceeds the budget. Adding a stage to simplify routing can cost more margin than the routing saved.

The test is straightforward: if the buffer is added for a timing or isolation reason, it is justified; if it is added because the router could not reach, it is a layout problem that has been converted into a timing problem. Recognising the difference is what separates a clock tree that works from one that is re-spun.

Verifying the Clock Tree

Verification should measure what the buffer does to the signal rather than only confirming that the net is connected. Phase noise or jitter measured at each branch, with the system in its normal operating state, is the evidence that the supply noise and the loading assumptions were correct. Measurements taken with a quiet bench supply prove very little.

If the measured jitter is worse than budgeted, the order of investigation is supply noise first, then loading, then the buffer configuration. At gopcb, clock nets and their reference planes are reviewed as a group, so that the supply and return path assumptions are visible on the drawing rather than buried in a constraint file.

Additional Considerations for This Build

Practical attention to signal integrity pays for itself here, because it decides whether the finished board behaves as the drawing intended. Where the requirement is not stated on the fabrication drawing or in the assembly notes, the shop has to assume a default, and that default is rarely the value the design was simulated with. Stating signal integrity explicitly, together with the tolerance that applies, removes the assumption and keeps the result predictable from batch to batch.

Process Control and Verification

Reviewing the design before the data is released is far cheaper than correcting it after the panel is in the tank, because every step downstream inherits the decision made at the front end. Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance.

FAQ

Does a clock buffer reduce jitter? Not usually. It re-drives the clock and isolates the source, and it adds its own jitter plus any converted from supply noise. It improves jitter only when it replaces a badly loaded direct drive.

How many buffers can a clock path tolerate? As few as the timing budget allows. Since jitter accumulates along the path, each stage should be justified by a loading, isolation or distance requirement that the previous stage cannot meet.

Where should the decoupling go? As close to the supply pins as the layout allows, with a short return to a continuous reference plane. Distance matters more than the value of the capacitor in most clock applications.