DDR Routing Topology: Point to Point, T Branch and Fly-by

A single memory device attached to a controller makes every net look like a point to point connection, and the layout rules are correspondingly simple. Add more devices or more ranks, and the nets stop being equivalent: the address and command lines become shared buses loaded by several receivers, while the data lanes remain local channels between the controller and one device.

Treating all of them as the same kind of trace because they are all fast produces a design that can be routed but not controlled. The branch points, the loading, the reflections and the order in which the signal arrives at each device are all decided by the topology, and the topology has to be chosen before the constraints are written.

Topology Is an Electrical Strategy

The difference between point to point, a T branch and fly-by is not how tidy the drawing looks. It is how many loads the driver sees, how long the branches are, and in what order the signal reaches each device. Each arrangement changes the transmission line branching, the reflections, the position of the terminations and the way timing has to be compensated.

Which of them is permissible depends on the controller, the memory generation and the devices involved, and the authoritative source is the design guide the manufacturer publishes for that combination rather than a general preference. Reading that guide before the schematic is finished prevents a re-layout later.

Why Data and Address Cannot Be Wired the Same Way

Data signals and their strobes form a local channel: the connection relationship is concentrated, the sampling reference travels with the data, and the net usually connects one transmitter to one receiver. Address and command signals often have to reach several devices, so they face a shared load by construction, and the clock or control signals may be shared in the same way.

The consequence is that the two groups need different constraints, and the layout review should treat them as two separate exercises rather than one. The data lane is concerned with impedance and with the relationship inside the channel. The shared bus is concerned with multiple loads, branch geometry and the arrival order at each device, and it needs termination and compensation decisions that the data lanes may not need at all.

What Each Topology Solves

Point to point connects one driver to one principal load. The branch content is minimal, the structure is direct, and the analysis is simple. It is the natural arrangement for the data lanes and for single device designs, but it cannot express a shared multi-load relationship.

A T branch splits from a common node out to several loads, which makes the arrival at the loads symmetric and keeps the relationship between devices conceptually clean. The cost is that the split itself is a discontinuity, and the branch stubs and the loads have to be included in the analysis rather than treated as a drawing detail.

Fly-by runs the signal along a main trunk past each load in sequence. It reduces the large split and is common on memory buses with several devices, but it produces a deliberate arrival order: the device nearest the driver sees the signal first. That ordering is not a defect, and it is the reason write leveling and read timing training exist in modern controllers, because the controller compensates for the skew it knows about.

None of the three is universally best. The memory generation, the organisation of the devices, what the controller supports, the termination scheme, the layer count and the available space all change the choice, and a design that ignores the controller support for a given arrangement will not be rescued by careful routing.

Why Equal Total Length Is Not Enough

Two nets with nearly identical total length can still differ in where the branches sit, how long the stubs are, how many loads they carry and how they are terminated. On a multi-load net the wave propagates and reflects at every discontinuity, so the arrival window depends on the complete topology rather than on the sum of the segment lengths.

Length constraints therefore rest on the topology being correct first. Choosing the wrong connection structure and then compensating with serpentine copper to equalise the lengths only produces a more complicated geometry with the same electrical error, and it makes the design harder to review.

The Order to Work In

Read the controller and memory design guides first and confirm which topologies, terminations and routing roles are supported. Separate the shared signals from the local point to point signals while the schematic is being drawn, rather than classifying them once the layout has begun. Then fix the topology and the termination placement according to the device count, the placement and the manufacturer requirement.

Build the constraint set from that: impedance, branch definition, arrival time and group relationships, not a single length rule applied to every net. After routing, verify the worst case with the device models, a simulation or the calibration results reported by the controller, and record which of the constraints were actually met. The stack-up itself, including the layer assignment that provides the reference planes for these nets, is a question for board fabrication and should be agreed before the constraints are frozen.

Write leveling and read training deserve explicit mention because they change what the constraint has to achieve. Where the controller trains the interface, the requirement shifts from equal absolute delay to a defined and bounded skew, and the fly-by topology becomes viable. That training is a measurement, and it belongs in the bring-up plan rather than being discovered at the customer site. Where the controller does not, the topology has to provide the alignment itself, which usually means a different structure.

Four Misreadings

Choosing a topology because it looks symmetric rather than because it suits the devices leaves the electrical behaviour undecided. Applying one rule set to the whole interface ignores the different roles of the shared bus and the local data channel. Counting only total length while ignoring branch points and stub lengths loses the information that determines the arrival window. Copying a previous project assumes the controller, the memory generation and the device organisation are the same, which they usually are not.

FAQ

Is fly-by always better than a T branch? It is common on multi-device buses and manageable because controllers compensate for the arrival order, but the design guide for the specific devices decides.

Do the data lanes need termination? Often a different treatment from the address bus, and on many modern interfaces the termination is inside the devices and configured rather than placed on the board.

Can serpentine matching fix a poor topology? No. It changes geometry, not the branch structure, the loading or the arrival order.

What should be verified after routing? The topology as built, the stub lengths, the impedance, the arrival order and the result of the controller training.

Summary

Routing a DDR interface starts with an electrical decision, not a routing decision. Choose the topology the controller and the memories support, separate shared buses from local channels, include the branches in the analysis, and build constraints that describe the topology rather than only its total length. Do that first, and the layout constraints describe a real structure instead of an approximation of one.