How to Tell a High-Speed Signal from a Low-Speed One in PCB Design

The question of which signals on a board are high speed and which are not comes up in every layout review, and it is usually answered with the clock frequency. That answer is wrong often enough to cause real problems, because the property that makes a signal difficult to route has nothing to do with how often it changes state and everything to do with how fast it changes state.

Frequency Is the Wrong Criterion

A signal that switches once per second can still be a high-speed signal if the transition between the two states takes half a nanosecond. The transition is what contains the high-frequency energy, and it is the transition that a trace has to carry without distorting.

The useful way to think about it is in terms of the spectrum of the edge. A rising edge that takes a nanosecond contains significant energy at frequencies far above the repetition rate of the signal, and the highest frequency that matters is roughly the one where the energy has fallen to about half, which is often approximated as one divided by twice the rise time. A clock at 10 MHz with a 1 ns edge therefore has meaningful content in the hundreds of megahertz, and a control line that toggles a few times a second with the same edge rate has exactly the same content.

That is why the design rules follow the edge rather than the clock. Two signals with the same rise time need the same treatment even if their frequencies differ by six orders of magnitude.

When a Trace Becomes a Transmission Line

The second criterion is length relative to the edge. A trace only behaves as a transmission line when the time the edge takes to travel down it is a significant fraction of the edge duration itself.

In a typical board material the signal travels at roughly six inches per nanosecond on an outer layer, which is about 150 mm per nanosecond, and slightly slower on an inner layer. The practical threshold that follows from this is about 25 mm of trace for each nanosecond of rise time, or one inch per nanosecond in the units the rule was originally written in. Below that length the trace behaves as a piece of wire, and above it reflections from the far end arrive back while the edge is still rising and start to distort it.

A 1 ns edge on a 20 mm trace is comfortable. The same edge on a 100 mm trace needs controlled impedance, a continuous reference plane and a termination strategy, even if the signal is a reset line that changes state twice a day.

The Symptoms of Getting It Wrong

When a signal that needs transmission line treatment is routed as a simple connection, the failures are specific and familiar.

Ringing on the edge is the first. An unmatched line reflects at both ends, and the reflections add to and subtract from the edge, which produces overshoot above the supply rail and undershoot below ground. The overshoot stresses the input protection of the receiving device, and the undershoot can forward bias a parasitic diode.

Double clocking is the second, and it is the one that appears as an intermittent functional failure. A clock line with ringing can cross the input threshold more than once per edge, so the receiving device sees two events where the driver sent one. Boards built from such a design often pass at room temperature and fail in the cold or at the end of a batch.

Crosstalk is the third. A fast edge couples into a neighbouring trace through the mutual capacitance and inductance between them, and the coupling depends on the edge rate rather than on the clock. A quiet line lying next to a fast one for a long distance will pick up a spike every time the fast one switches, and whether that matters depends on the receiver.

The fourth symptom has no electrical signature at all: radiated emissions. A trace carrying a fast edge with a poor return path forms a loop that radiates, and the loop area is set by the geometry rather than by the signal. This is why a low-frequency signal with a fast edge has to be routed with a return path in mind. How much of that path can be planned on the board depends on the stack-up, because a ground plane adjacent to the signal layer provides the return current without any extra copper; the layer arrangements available are listed on our PCB capabilities page.

What Makes a Signal Easy to Route

Working backwards from the two criteria gives a practical classification.

A signal is easy when its rise time is long compared with the time it takes to travel its own length, and when its destination is close to its source. Slow edges, short traces and generous spacing remove almost every problem.

A signal is difficult when the edge is fast relative to the trace length, when the trace has to cross a split in its reference plane, when it must pass through a connector, or when it has to change layers. Any one of those conditions means the trace needs an impedance target, a reference plane and a deliberate return path.

The awkward cases are between the two, and they are the ones that produce arguments. A reset line that runs across a large board, a clock that feeds several devices along a long spine, an enable signal that passes through a wire harness: each is slow by frequency and fast enough by edge rate to need care. The resolution is to look at the driver datasheet and use the rise time rather than the intended frequency.

Practical Checks Before Routing

The classification is worth doing as a list rather than as an opinion, because it drives the routing rules.

Start with the driver data sheet. Take the rise time for each device output, convert it into a critical length using the material velocity, and compare it with the longest possible route the signal can take. That comparison produces a list of nets that need an impedance target, and everything else can be routed without one.

Add the signals that share a path with a fast net, even if they are slow themselves, because crosstalk is a property of the pair rather than of the individual trace. A slow input line running beside a fast clock for a hundred millimetres is a fast problem.

Include the connector and cable paths in the same analysis. A board-to-board link that carries a fast edge through a connector has a discontinuity at the connector that will show up as a reflection regardless of what happens on the board. Where a design is prototyped before production, that is worth testing early, and our rapid PCBA prototyping builds give a quick way to compare a measured eye diagram against the layout assumption.

Finally, write the result into the design rules rather than into a conversation. A net class for the high-speed nets, with its own width, spacing and via rules, carries the classification through every later edit, including the ones made by someone who was not in the review. Our layout review checks that the rules and the routing agree before the data is released.

FAQ

Is a 100 MHz clock always a high-speed signal? Not necessarily. What matters is the rise time and the length of the route. A short trace with a slow edge can carry a 100 MHz clock comfortably.

Is a low-frequency signal ever high speed? Yes. A signal that switches a few times a second with a sub-nanosecond edge has the same high-frequency content as a fast clock and needs a controlled return path.

What is the single most common mistake in this area? Treating the clock frequency as the criterion, which leaves fast edges with slow names routed as if they were DC.