Design for Test on PCB Layouts

What Design for Test Means

Design for test is the practice of making a board easy to verify while it is still being laid out. It covers test point access, the placement of alignment features, the routing that lets a tester isolate a node, and the support for built-in test capability in the devices on the board. It is a layout activity, not a test activity, because once the board is fabricated the available coverage is largely fixed.

The cost of ignoring it is paid later. A net with no test access cannot be covered by any fixture or probe, and by the time the gap is discovered the layout is committed and the only remedies are manual inspection, a functional test that may not detect the fault, or a redesign. Each of those is more expensive than a test point.

Design for test also reduces the time spent on debugging. A board with good test access produces a specific diagnosis when it fails; a board without it produces symptoms that have to be traced by hand.

Test Point Placement Rules

The first rule is that every net should have at least one accessible point, preferably on the side the fixture probes. The point should be a dedicated pad where possible, large enough for the probe tip and spaced from its neighbours so that probes do not interfere with each other or with components.

The second rule is that test points must be clear of components. Tall or oddly shaped parts prevent the board from seating on a fixture and can block a probe from reaching a nearby point. Components on the probed side are particularly problematic, so test points are usually placed on the side that will remain clear or in areas where the parts are low profile.

The third rule concerns the electrical effect of the point itself. A test pad adds capacitance and a short stub, which is harmless on most nets and significant on a high-speed line. Where a point cannot be avoided on a sensitive net, it should be as small and as short as possible, and its effect should be included in the signal integrity analysis.

Fixture and Probe Constraints

Test points should be arranged on a grid that suits the fixture, because the cost of a bed of nails rises sharply with irregular spacing. Keeping points on a standard pitch and avoiding clustering makes the fixture simpler and cheaper and reduces probe interference.

Tooling holes and fiducials provide the mechanical reference that both the assembly machine and the tester need. They should be placed in areas that will not be populated and should be sized to the standard pin, and they should be present on a known pair of diagonal corners if the machine uses two references.

Board stiffness matters as well. A thin or flexible board that flexes when pressed onto a fixture can fail to contact some probes, so stiffeners, rails, or support areas may be needed. If the board will be held by its edges, the edge features should be strong enough to take the clamping force.

Supporting Boundary Scan

Boundary scan shifts some test coverage from physical probes into the silicon. Devices that support it can drive and observe their own pins through a scan chain, which reduces the number of test points needed and allows coverage of nets that are otherwise inaccessible. Supporting it means daisy-chaining the scan devices correctly, providing access to the scan pins, and making sure the chain can be isolated from the rest of the circuit during test.

The design has to include the chain as a deliberate feature. A scan chain that is broken by an inaccessible device or that shares a net with other logic cannot be used reliably, and the loss of coverage will not be obvious until the test program is developed.

Where boundary scan is used, the test engineer should be involved during layout so that the chain is planned and the necessary access is provided. Adding it after the layout is complete usually means accepting reduced coverage.

Test Coverage as a Design Metric

Coverage should be estimated during layout rather than measured after the fixture is built. A simple count of nets with accessible test points, reviewed against the netlist, gives an early indication of where the gaps will be. Nets with no access can then be addressed by adding a via, moving a point, or accepting the gap with a documented reason.

The estimate should distinguish between nets that will be tested by the fixture and nets that will be covered by another method, such as boundary scan or a functional test. A net that is covered by two methods is a lower risk than one that is covered by neither, and the review should make that visible to the team.

Where the product is safety related or high reliability, the coverage estimate becomes part of the design record. A documented coverage number with a list of untested nets is far more useful than an assumption that the test will find everything.

Coordinating With the Test Engineer

Design for test works best when the test engineer reviews the layout before it is released. That review should cover test point access, the arrangement of points on a grid, the placement of tooling holes and fiducials, the boundary scan chain, and the areas that will be coated or potted and therefore inaccessible to a probe.

The review should also consider the side of the board that will be probed and whether components on that side will obstruct the fixture. Deciding the probe side early allows the layout to keep that side clear, which is much easier than adjusting it later.

Finally, the review should confirm that the test points will remain accessible after assembly. A test point that is covered by a connector, a shield, or a coating cannot be probed, and that is a common way for coverage to be lost between layout and production.

FAQ

Do I need a test point on every net? Ideally yes, on the side the fixture probes. Where a net has no accessible point, the coverage gap should be documented and covered by another method if possible.

How large should a test point be? Large enough for the probe tip being used and spaced so that neighbouring probes do not interfere. The fabrication and assembly houses can provide the minimum sizes their equipment requires.

Can test points be placed on high-speed nets? They can, but they add capacitance and a stub. Where they are necessary, keep them small and short and include the effect in the signal integrity analysis.

What is boundary scan used for? It lets compatible devices drive and observe their own pins, providing coverage without physical probes. It reduces the number of test points needed but has to be planned during layout.

When should the test engineer be involved? During layout, before the design is released. Coverage is largely determined by the layout, so later involvement can only document the gaps rather than close them.

Conclusion

Design for test is a layout discipline that decides how much of a board can ever be verified. Accessible test points on a sensible grid, clear areas for the fixture, tooling holes and fiducials in the right places, and a planned boundary scan chain together raise coverage before the first panel is built. Reviewing the layout with the test engineer turns that into a documented number rather than an assumption. For the surrounding process, see our notes on PCB design and layout, PCBA testing, PCB assembly, and quality management for how test strategy is planned in 2026.