Signal Integrity Budget for PCB Designs

A signal integrity budget is an allowance made before layout begins, in which the total margin available in a design is divided between the effects that will consume it. The alternative, which is what most projects actually do, is to lay out the board and then find out whether it works. The budget takes an hour to construct and it changes the routing decisions that follow, because a designer who knows that reflections may consume two hundred picoseconds routes differently from one who does not.

What the Budget Contains

The budget starts from the timing margin that the design has available, which comes from the interface specification and the clock arrangement. From that total, allowances are subtracted for the effects that are known to occur: the skew between signals, the propagation delay of the traces, the rise time degradation from loss, the reflection from impedance discontinuities and the jitter of the source and the receiver.

Each of those terms is estimated rather than measured at this stage, which is acceptable because the purpose is to show which terms dominate. In a short, slow design one term will consume most of the margin; in a long, fast one the losses and the reflections may take nearly all of it. Knowing which case applies changes where the design effort should go.

The budget should be written down and kept with the design documents. A budget that exists only in a conversation cannot be checked later, and the first question after a failure is always whether the allowances were realistic. Recording the assumptions with the fabrication notes makes the finished board a reference for the next design.

Rise Time and Bandwidth

Rise time sets the bandwidth that the interconnect has to pass, and it is the single most important number in the budget. A signal with a fast edge contains high frequency content regardless of its repetition rate, so a slow clock with a fast driver can require more from the board than a fast clock with a slow driver. The edge, not the clock, is what the trace has to carry.

The practical rule is that the interconnect behaves as a transmission line when the propagation delay of the trace is a significant fraction of the rise time. Below that threshold the reflections settle before the receiver samples and the design is tolerant; above it the reflections arrive during the transition and the design needs controlled impedance and termination.

Rise time is also degraded by the loss of the material and by the length of the trace. A long trace with a lossy dielectric will round off the edge, which reduces the high frequency content and can cause the receiver to misjudge the timing. The same mechanism attenuates the fast edges that the receiver needs to resolve, and it is the reason that loss appears in the budget as a timing term as well as an amplitude term.

Reflection and Termination

Reflection occurs wherever the impedance of the path changes. A change of trace width, a via, a connector, an unloaded branch or a poorly terminated end all produce a reflection, and each reflection consumes part of the budget. The largest single cause is usually the mismatch between the driver, the trace and the receiver, which is why termination is the classic answer.

Termination can be series, parallel, or a more elaborate arrangement such as a Thevenin or an active terminator, and the choice depends on the drive strength, the number of receivers and the power budget. A series resistor at the driver is inexpensive and effective for a single point to point connection, while a parallel terminator at the receiver is better for a bus, at the cost of continuous current.

The budget should account for the fact that unloaded vias and stubs behave as short transmission lines. A stub that is electrically short relative to the rise time is harmless, and the same stub becomes a reflection source when the edge becomes faster. This is why a design that works at one speed may fail when the same board is fitted with a faster driver.

Loss and the Material

Loss in a PCB comes from the conductor and from the dielectric. The conductor loss rises with frequency because of the skin effect, and the dielectric loss rises with both frequency and the loss tangent of the material. At moderate speeds the conductor loss dominates, while at high speeds the dielectric loss becomes the larger term and the choice of laminate starts to matter.

The budget should reflect the length over which the signal has to travel. A short trace on a standard laminate can be entirely adequate at a speed where the same signal on a long trace would need a low loss material. This is why high speed designs often use a low loss material selectively, on the longest routes, rather than across the whole board.

Copper roughness contributes as well, and it becomes significant at high frequencies where the current is confined near the surface. A smooth foil reduces the loss, and the difference is measurable on a long channel. This is one of the cases where the material specification has a direct effect on a timing budget that was set months earlier.

Crosstalk and Other Terms

Crosstalk consumes budget in a way that is different from the others, because it depends on the routing rather than on the material. Parallel traces running close together over a distance couple energy from one to the other, and the coupled noise appears as an apparent shift in the timing of the victim signal. The budget should include an allowance for it, and the routing rules should be chosen to keep within that allowance.

The standard responses are spacing and reference. Separating aggressive signals from sensitive ones, keeping a continuous reference plane beneath the traces and avoiding long parallel runs remove most of the coupling. Where a bus must run in parallel, the spacing of three times the dielectric thickness is a common starting rule, and the actual figure should be checked for the speeds involved.

Ground bounce and simultaneous switching noise belong in the same category. They arise when many outputs switch at once and the return path has enough inductance to develop a voltage, and they appear as an apparent change in the reference level. The remedy is a well designed power and ground structure with adequate decoupling, which is designed rather than added at the end.

Timing Budget in Practice

The timing budget is applied by listing the terms, assigning a maximum allowance to each and checking that the total remains inside the margin. Where a term is not estimable, it should be bounded rather than ignored, because an unbounded term will consume whatever margin exists. The usual result of the exercise is that one or two terms dominate and the rest can be treated as a fixed overhead.

The allocation then becomes a design constraint. If the reflection allowance is two hundred picoseconds and the trace delay is one hundred and seventy picoseconds per metre, the length of the route that can be left unterminated follows directly. Designers find this far more useful than a general instruction to route carefully, because it gives a number to work with.

The budget should be revisited when the design changes. A faster driver, a longer route or a different laminate can move a term from negligible to dominant, and a budget that is not updated becomes an obsolete document that nobody consults. Keeping it with the design revision makes the update natural.

Practical Rules

Set the budget before layout, base it on the fastest edge rather than the clock frequency, and record every assumption in the design documents. Bound the terms you cannot estimate, and update the budget whenever the design changes.

Verify the finished board against the budget, using a coupon or a test structure where the design justifies it, and compare the result with the quality data from production. Signal integrity work is most effective when it is done as an allocation exercise before routing, because after the boards are built the only remaining options are expensive ones.

FAQ

What is a signal integrity budget? An allocation of the available timing and amplitude margin across the effects that will consume it, made before layout rather than discovered afterwards.

Why does rise time matter more than clock frequency? Because the fast edge carries the high frequency content. The interconnect has to pass the edge, not the repetition rate.

When is termination needed? When the trace delay is a significant fraction of the rise time, so that reflections arrive while the receiver is still sampling.