16-Layer PCB: Stack-Up and Manufacturing Limits

What Changes at Sixteen Layers

A sixteen layer board differs from a twelve layer board by more than four layers. The board is thicker, the through vias are longer, the accumulated registration error across the stack is larger, and the number of process passes makes the yield the dominant cost. At this layer count the design and the fabricator have to work from the same stack drawing, and the plant has to be capable of building it rather than willing to try.

Boards of this class appear in high speed networking equipment, in instrumentation and test equipment, in radar and satellite systems and in professional computing. The circuits have in common a large package with many connections, several fast interfaces, multiple supply rails and a requirement that every high speed signal has a continuous reference.

Stack-Up

The stack is symmetrical and is built from a repeating pattern. A typical arrangement is a ground plane, a signal layer, a signal layer and a power plane, repeated with the plane assignment adjusted so that the fastest interfaces have the best reference. Sixteen layers usually yields ten signal layers and six planes, or twelve signal layers and four planes where the routing density demands it.

Three constraints govern the arrangement.

Symmetry. The construction above the mechanical centre matches the construction below it. On a thick board the warpage from an unbalanced stack is severe and cannot be corrected afterwards by the assembly process.

Copper balance. The copper area on each layer should be broadly similar, and where one layer must be sparse a balancing pattern is added. A board with heavy copper on the power layers and light copper on the signal layers bends during lamination.

Reference continuity. Each high speed signal has a plane adjacent to it on the layer it runs in, and where a signal changes layer a return via is placed beside it. On a thick board the distance between the layers makes that transition more significant, not less, so the number of transitions is minimised by planning the interface routing as a whole. Our notes on PCB design and layout describe the routing techniques.

Vias and Back Drilling

A through via in a board of two or three millimetres has a stub that is a real electrical length. At the highest data rates that stub produces a notch in the insertion loss and a reflection that degrades the eye. Three techniques are used, and they are usually combined.

Back drilling. After lamination and plating, the unused barrel is drilled away from the appropriate side. It removes the stub, costs one extra drilling operation per back drilled layer pair, and requires the drill depth to be controlled so that it does not cut into the layers the via serves. It is the workhorse of high speed backplane design.

Blind and buried vias. Vias formed between inner layers during a sequential lamination cycle. They eliminate the stub and free routing space on the layers the through via would have crossed. Each additional lamination cycle adds cost and reduces the yield, so they are used where the density demands them.

Microvias. Laser drilled vias used to escape a fine pitch package into the inner layers. They give the greatest density and require the filling and plating sequence when they sit in a solderable pad.

Materials

The layer count and the assembly thermal load push the material selection before the electrical requirement does. A sixteen layer board is thick, and a thick board absorbs more heat during reflow and warps more if the laminate softens, so a high glass transition temperature laminate is used as the starting point.

On top of that, the loss budget decides whether a low loss material is needed on the layers carrying the fastest signals. A hybrid stack with the speciality laminate on four or six layers and ordinary laminate elsewhere is the usual answer, because the speciality material is expensive and there is rarely a reason to use it on a power plane. Our notes on PCB capabilities describe the limits of the process.

Impedance control is mandatory on a board of this class. The stack is simulated to the target impedance, the coupon is built on the production panel, and the measurement is part of the delivered data. Where a hybrid stack is used, the coupon has to include the speciality material, because that is where the impedance error will appear.

Manufacturing

The process is a sequence of image, etch, inspect and laminate passes, and the cost is essentially the number of passes. Each inner layer is inspected before it is buried, because a defect inside a sixteen layer stack is not repairable. Registration is controlled across the panel, and the material movement during each lamination cycle is predicted and compensated.

The drilling programme mixes mechanical through holes, back drilled holes and blind or buried vias formed in the earlier lamination cycles, and all of them have to register to the same pattern. The plating has to fill the microvias and plate the deep through holes uniformly, which are different requirements in the same cycle.

Inspection is comprehensive: automated optical inspection of the inner layers, X-ray of the registration and the back drilling where it matters, a microsection of the finished board to confirm the plating thickness and the hole wall, and the impedance coupon. A first build on a board of this class is a prototype exercise whatever the volume, and the coupon data is examined before production is released. Our notes on PCB manufacturing describe the process, and our notes on quality management describe the controls.

Cost and Schedule

The price is driven by the number of passes, the panel utilisation, the via complexity and the yield. A sixteen layer board costs several times a six layer board of the same outline, and the multiple grows with anything that adds a process cycle: blind vias, back drilling, heavy copper and fine line geometry.

Schedule is the other constraint. The material has to be ordered, the lamination cycles are scheduled in sequence, and the inspection and coupon measurement add time at the end. A lead time measured in weeks rather than days is normal, and an expedited build is usually a matter of prioritising the existing sequence rather than of shortening it.

The comparison that matters is against the alternative architecture. A design that needs sixteen layers to route a package often has an alternative with a different package, a different memory arrangement or a different board outline. Where the layer count can be reduced by a system decision, the saving is larger than any negotiation with the fabricator.

Design Practice

• Agree the stack with the fabricator before the routing. The layer assignment, the material and the thicknesses come from the plant as much as from the designer.
• Keep the stack symmetrical and the copper balanced. On a thick board this is not optional.
• Minimise layer transitions on high speed nets. Every transition is a stub, a reflection and a return via.
• Use back drilling before blind vias. It solves the stub problem at a fraction of the cost for most designs.
• Plan the power delivery. A thick stack has a long path from the capacitor to the die, and the inductance of that path is part of the power integrity design.
• Ask for the data. The coupon measurement and the microsection should accompany the first boards, and our notes on PCBA testing describe how the finished assembly is verified.

FAQ

How many signal layers does a sixteen layer board have? Typically ten to twelve, with the rest used as ground and power planes.

Is back drilling always needed? No. It is used on the nets where the stub would degrade the signal, which is usually the fastest interfaces and the longest through vias.

What is the typical thickness? Two millimetres and upwards is common, and the finished thickness is set by the number of layers and the dielectrics between them.

How long does it take to build? Several weeks from material order to shipment is normal, and the coupon measurement and inspection are part of that schedule.

Conclusion

A sixteen layer board is a manufacturing programme as much as a design. Agree the stack with the plant, keep it symmetrical and balanced, minimise the layer transitions on the fast nets, back drill before adding blind vias, and insist on the coupon and microsection data with the first build. Where the circuit allows the layer count to be reduced by a system decision, that saving beats anything the fabrication negotiation can produce.