Power Integrity on a PCB: The PDN From Bulk to Die

Power integrity is the least visible part of signal integrity and the most common cause of intermittent failures. A board can pass every eye diagram test and still reset a processor when an FPGA switches a thousand outputs at once, because the supply voltage at the die moved further than the tolerance allows. The problem is not the regulator: it is the impedance of the path between the regulator and the die.

What Power Integrity Means

The objective is straightforward. The voltage at every device pin has to stay inside the tolerance the device specifies, at every frequency the device draws current, including transient events that last nanoseconds.

The current a modern device draws is not a steady value. A processor draws almost nothing while idle and then demands tens of amps within a few nanoseconds when a block wakes up. The supply has to deliver that current through a network of capacitance, planes and traces, and the network has a finite impedance at every frequency. When the transient current meets that impedance, the voltage moves by the product of the two, and if the movement exceeds the tolerance, the device malfunctions.

This is why power integrity is treated as an impedance problem rather than a voltage problem. The regulator holds the average voltage correctly; what the network does at high frequency is what determines whether the rail is quiet.

Target Impedance

The standard technique is to define a target impedance and design the network to stay below it across the frequency range of interest.

The target is calculated from the allowed ripple and the worst case current step: a rail allowed 50 millivolts of noise and subject to a 10 amp step needs a network impedance below 5 milliohms at the frequencies where that step occurs. That number is a hard constraint on the design, and it is usually the reason a board needs more capacitance, a thinner dielectric between the planes, or a different stackup.

What matters is the shape of the impedance curve rather than its average. A capacitor provides low impedance over a limited frequency band and becomes inductive above its self resonant frequency, so a network is built from several values to cover a wide band. When the curve has a peak above the target, the rail will oscillate at that frequency, which is why anti resonance between two capacitor banks is a real concern and not a theoretical one.

The Three Frequency Ranges

It helps to think of the network as three stages, each of which handles a different part of the frequency spectrum.

Bulk capacitance covers the low frequencies, from a few kilohertz to a few hundred kilohertz. Large electrolytic or polymer capacitors near the regulator hold the rail steady through slow load changes and supply the average current the switching converter cannot deliver instantly. Their value is measured in tens or hundreds of microfarads, and their placement is not critical because the frequencies involved are low.

Bulk and mid frequency decoupling covers roughly a hundred kilohertz to a few megahertz, and this is where the plane pair and the larger ceramic capacitors do the work. The plane pair formed by a power layer and an adjacent ground layer behaves as a distributed capacitor, with a capacitance proportional to the dielectric constant and the area, and inversely proportional to the separation. A thin dielectric between the two layers is a direct way to raise that capacitance without adding components.

High frequency decoupling covers everything above a few megahertz, and it is dominated by the small ceramic capacitors placed at the device, by the inductance of the connections to them, and ultimately by the capacitance inside the package and on the die itself. Above a few hundred megahertz, the die and package capacitance supplies the current, which is why the board design cannot fix a problem that originates inside the package.

Loop Inductance and Placement

At high frequency, the limiting factor is rarely the capacitor value. It is the inductance of the loop formed by the capacitor, the vias, the planes and the device pin.

A 100 nanofarad capacitor has an inductance of about 0.5 nanohenries in its own package, which gives a self resonant frequency in the region of 20 megahertz. The connection adds more: two vias of 1 mm contribute around 1.5 nanohenries, and a trace of a few millimetres contributes more than that. The practical consequence is that the connection often dominates the component, which is why the rules about placement focus on the loop rather than on the value.

Three rules follow. Place the capacitor as close to the pin as the layout allows, with the smallest possible loop between the capacitor pads and the two planes. Use the shortest and widest connection available rather than a thin trace. And connect to the planes with vias placed immediately at the capacitor pads, not at the end of a short trace, because every millimetre of trace adds inductance. Our article on decoupling capacitor placement works through those geometric details.

The plane pair also contributes inductance, in the form of spreading inductance between the via where the current enters the plane and the device it feeds. On a large board with thin dielectric, this is usually small compared with the connection inductance, but it is not zero, and it is the reason a plane is not a perfect conductor at gigahertz frequencies. Our guide to power plane design covers how the plane geometry and the choice of layer pair affect it.

Stackup Choices

Two stackup decisions determine most of what the plane pair can do.

The first is the separation between the power layer and the adjacent ground layer. Capacitance rises as the separation falls, so a 0.1 mm dielectric has several times the capacitance of a 0.4 mm layer, and that capacitance is distributed across the whole board rather than concentrated in a component. It also reduces the spreading inductance, because the fields between the planes are tighter.

The second is the layer order. Placing the ground plane immediately next to each power plane, rather than several layers away, gives the return current a short path and gives the pair its capacitance. A design where the power plane is separated from ground by two signal layers loses most of the benefit, both electrically and in terms of the return path for high speed signals.

The trade is mechanical. A thin dielectric between planes is more expensive to laminate and can make the board harder to keep flat, and a stackup with power and ground layers adjacent reduces the number of layers available for routing. Those costs are the reason the decision belongs in the stackup discussion rather than in a later optimisation, and why the fabricator should be involved before the layer assignment is fixed.

Ground Bounce and Simultaneous Switching

When many outputs of a device switch at the same time, the current that flows through the package and the board return path develops a voltage across the inductance of that path. The local ground reference moves, which is called ground bounce or simultaneous switching noise, and a receiver that is referenced to that ground sees a shifted threshold.

The board contribution to that effect is the inductance of the return path between the device and the plane, and it is reduced by the same measures that improve the power network: more ground vias directly under the device, closer plane pairs, and a solid plane with no splits beneath the component. It is also the reason a ball grid array with a large number of ground balls performs better than the same die in a package with fewer.

Ferrite Beads and Split Planes

Two techniques that are popular for isolating analog and digital supplies deserve caution.

A ferrite bead in a supply line forms a filter with the capacitance on either side of it, and that filter has a resonance. If the damping is poor, the combination can amplify noise at the resonant frequency rather than attenuate it, which is a known failure mode in mixed signal designs. Any bead should be checked together with the decoupling on both sides rather than chosen by its impedance at one frequency.

Splitting a plane into analog and digital sections is the second. The intent is to stop digital noise reaching the analog circuit, and the effect is often the opposite, because the return current for a signal crossing the split has to divert around it. That detour increases the loop area, which increases emissions and crosstalk, and it makes the two grounds move relative to each other. Where a split is used, the signals that cross it need their own return path, and the two grounds must be joined at a single defined point. Our article on layout rules covers the general case of return path continuity.

Verifying the Network

Power integrity is measured rather than simulated alone, and two measurements are practical on a real board.

The first is the impedance of the power delivery network, measured with a vector network analyser between the rail and ground at a point near the device. The result is a curve of impedance against frequency, and it can be compared directly with the target. This measurement identifies the resonant peaks, the effect of the capacitors and the point at which the plane pair takes over from the discrete components.

The second is the voltage ripple at the device under real load, measured with a wideband probe and a short ground connection. A long ground lead on an oscilloscope probe adds inductance that hides the very high frequency content, so a probe with a spring ground or a coaxial connection is required for a meaningful result.

Both measurements benefit from being planned at the design stage. A test point on the rail near the device, with a ground point beside it, costs nothing at layout time and makes the measurement possible later. Without it, the measurement either cannot be made or has to be taken at a distance that changes the answer.

Design Rules

• Calculate the target impedance from the allowed ripple and the worst case load step, and keep the network below it across the frequency range.
• Place small decoupling capacitors at the device pins, with vias at the pads and the shortest possible loop to the planes.
• Keep the power plane adjacent to a ground plane in the stackup, and use the thinnest dielectric the process allows for that pair.
• Provide a continuous ground reference under every component, with no splits and no slots in the return path.
• Distribute ground vias around high current and high speed devices rather than relying on a few at the corners.
• Check any ferrite bead together with the capacitance on both sides for resonance, and damp it if the network peaks.
• Where a plane is split for isolation, provide a return path for every signal that crosses, and join the grounds at one point.
• Add test access to the rail near the critical devices for impedance and ripple measurement.

FAQ

• Do more capacitors always improve power integrity? No. Additional capacitance can create a new resonance with the existing network, so the network is designed as a whole rather than by adding parts.
• What causes a peak in the impedance curve? An anti resonance between two banks of capacitance, or between a capacitor bank and the plane capacitance. Damping, or a change in values, is the remedy.
• Is a plane pair enough on its own? It provides distributed capacitance at high frequency, but it cannot replace bulk capacitance for slow load changes.
• How thin should the power to ground dielectric be? As thin as the process allows and the mechanical design tolerates. The thinner it is, the higher the plane capacitance and the lower the spreading inductance.

Summary

Power integrity is an impedance problem. The regulator supplies the average current, and the network between the regulator and the die has to hold the impedance below a target across the frequencies the device draws. Bulk capacitance handles the slow changes, the plane pair and the larger ceramics handle the middle, and the small capacitors at the pin handle the fast edges within the limits of their connection inductance.

The design levers are geometric: close placement with short loops, adjacent power and ground layers with a thin dielectric, a continuous return path, and enough ground vias to keep the reference stable. Those choices belong in the stackup and layout decisions, and they should be checked against the capability of the process before the design is released, because a thinner power to ground dielectric is a fabrication requirement rather than a schematic one.