WMCM Packaging and the Shift to Substrate-Level Mainboards
On August 20, 2026, NDTV Profit cited supply chain information indicating that an image purporting to show an iPhone 18 Pro mainboard points to a new package architecture for the A20 Pro chip, with a noticeably larger neural processing area than the previous generation. Combining several supply chain reports, the A20 Pro is expected to use TSMC’s N2 2 nanometer process and to introduce wafer-level multi-chip module packaging for the first time in the product line, with reported performance gains of up to roughly 18 percent over the A19 Pro and efficiency improvements of around 30 percent. The board image and some parameters remain unconfirmed supply chain claims rather than official statements, but 2 nanometer process technology and WMCM packaging have become a clear direction for the next smartphone chip generation.
Chip Upgrades Are Moving From Process to Packaging
For most of the smartphone era, SoC advancement followed a single main line: process node scaling. That path is becoming harder and more expensive as it approaches 2 nanometers, and advanced packaging has emerged as a second lever with comparable leverage.
The conventional package-on-package approach stacks DRAM above the processor. It is mechanically compact, which is why it has dominated mobile designs for so long, but it concentrates heat in a small volume. Thermal management becomes progressively harder as power density increases, and the memory interface between the two stacked components has to operate in an environment where the processor is already the dominant heat source.
Wafer-level multi-chip module packaging takes a different approach. The SoC and DRAM are integrated more deeply at the wafer level, reorganizing the relative position of the dies and the interconnect relationship between them. That reorganization improves data transfer characteristics, power consumption and thermal behavior together, because the engineers designing the package are no longer constrained by a strict vertical stacking arrangement.
For the mainboard, this means the challenge is not simply a faster chip. Package form factor, input and output density and power integrity all change at the same time. As on-device AI models continue to grow, data exchange between CPU, GPU, NPU and memory increases substantially, and the escape routing space available in high density BGA regions shrinks further. That directly increases the importance of high density interconnect, any-layer structures, laser microvias and denser stackups.
Mainboards Are Approaching Packaging-Level Precision
High end smartphone boards have long been a major application market for HDI technology, and WMCM is likely to push mainboards toward even finer circuitry. As package I/O counts increase and pad pitch decreases, the space available for conventional subtractive etching processes narrows. This raises the value of mSAP and of line widths below 0.075 mm, while blind and buried vias, via-in-pad structures and higher order HDI stackups take on more of the layer-to-layer interconnect burden.
The change is not limited to line density. WMCM improves thermal coupling within the chip, but that does not reduce the importance of thermal design on the board. If the efficiency gains from a 2 nanometer process are converted into additional on-device AI performance, then localized heat flux, power integrity and high speed signal integrity all still need to be addressed systematically.
Thermal pads, copper distribution, thermal vias and high speed differential impedance control therefore have to be considered within one design framework rather than handled by separate teams in sequence. A stackup optimized purely for impedance may distribute copper in a way that concentrates heat, and a stackup optimized purely for thermal spreading may alter the impedance of adjacent high speed layers. On modern mobile boards, those two goals interact continuously, and reviewing that interaction during PCB design and layout is what prevents late-stage redesign.
The Boundary Between PCB and Packaging Is Shrinking
The wider significance of wafer-level multi-chip module packaging is that the technical distance between PCB manufacturing and advanced packaging continues to shorten.
IC substrates, substrate-like PCBs and high order HDI are all, in essence, the same progression: increasing line precision, finer via structures and higher interlayer interconnect density. When terminal chips enter the 2 nanometer generation, a board manufacturer’s competitiveness increasingly depends on the combined capability of laser drilling, precision exposure, plating and via filling, layer-to-layer registration, impedance control and high density SMT assembly.
No single one of those capabilities is sufficient. A supplier that can achieve fine lines but cannot control plating uniformity will fail on via quality. A supplier that can drill microvias but cannot hold registration through multiple lamination cycles will fail on high order stackups. The competitive question is whether the whole sequence holds together at production volume, which is a process integration problem rather than a single specification.
Why Fine Lines Alone Are Not Enough
It is easy to reduce the packaging convergence story to a line width number. That would miss the practical difficulty.
As features shrink, the sensitivity of the process to material dimensional change increases. Laminate expands and contracts during lamination and thermal cycling, and at 0.075 mm and below, that movement consumes a significant share of the available tolerance budget. Registration accuracy therefore has to be managed across the entire panel rather than at a few reference points.
Microvia alignment follows the same logic. A laser drilled via that misses its target pad by a small amount introduces a partial connection that may pass electrical test at room temperature and fail after thermal cycling. Plating uniformity across the panel determines whether via resistance is consistent enough to support impedance controlled high speed links. Each of these factors is individually manageable and collectively demanding.
Impedance control on fine line high speed channels adds a further constraint, because trace cross section becomes small enough that plating thickness variation measurably changes characteristic impedance. In that regime, controlling impedance within a narrow window requires the plating process itself to be controlled, not merely the artwork. This is where PCB fabrication capability measured across a full production panel becomes more informative than a specification sheet quoting a best-case line width.
The Same Trend Is Spreading Beyond Smartphones
High density interconnect demand is not confined to flagship phones, and the direction is consistent across several industries.
AI servers are moving toward 16 to 78 layer boards with high speed low loss materials and differential impedance control in the plus or minus five percent range. 800G and 1.6T optical communication equipment continues to push mSAP and fine line capability upward. Intelligent vehicle domain controllers, robot controllers and low altitude aircraft require HDI, high layer count boards, heavy copper high power design and high reliability assembly simultaneously.
Behind these different product categories, the underlying direction converges. As chip integration rises, the functional burden on the PCB increases. High speed systems demand lower loss. Power systems demand greater current carrying capacity. Wearables and robots need flexible and rigid-flex circuits to solve interconnect problems in three dimensional space. The board is evolving from a single-purpose connection carrier into a coordinated platform for signal, power, thermal and structural functions.
This is also visible in how AI hardware PCBA programs are specified. The compute board, the power board and the interconnect are increasingly designed together, because decisions made in one constrain the others, and separating them across suppliers makes the constraint conflicts harder to resolve.
What This Means for Manufacturing Strategy
For most manufacturers, the realistic response is not to attempt entry into flagship smartphone supply chains. It is to build and prove the underlying capability base that high density products require, because that base transfers across many product categories.
Concretely, that means fabricating in the range of 1 to 40 layers, covering HDI and any-layer structures alongside high frequency and high speed boards and flexible or rigid-flex circuits, achieving minimum line width and spacing around 0.076 mm, and controlling differential impedance within plus or minus five percent in applicable high speed scenarios. Those capabilities serve on-device AI products, robotics, communications equipment and industrial control across research validation and small to medium volume production.
Assembly capability is part of the same requirement. Fine line boards with dense BGA packages need SMT PCB assembly with placement accuracy and reflow control matched to package complexity, and inspection steps including solder paste inspection, automated optical inspection and three dimensional X-ray that can verify joints beneath packages. Under a quality management system that retains lot level records, a shift detected at final test can be traced back to the specific material or process step that produced it.
The Real Message
The meaningful signal in the shift from package-on-package to wafer-level multi-chip modules is not the name of a packaging technology. It is that advanced process nodes, advanced packaging and high density PCB manufacturing are simultaneously compressing the physical boundaries of electronic systems.
When chips enter the 2 nanometer generation and on-device AI continues to raise compute demand, mainboard manufacturing moves beyond high density routing toward coordinated design across package, board and assembly. The value of high order HDI and precision manufacturing will continue to rise accordingly, and the suppliers positioned to benefit will be those whose process control is documented across production volume rather than demonstrated on a single sample.
For engineering teams, the practical step is to treat the board as part of the package solution rather than as a passive carrier for a finished component. Decisions about stackup, via structure, copper distribution and thermal path made during layout determine whether the packaging advantages that a new chip generation delivers are actually realized in the finished product.
