Timing Analysis in High-Speed PCB Design

Timing analysis is the part of high-speed design that decides whether a bus will actually work, and it is the part most often skipped because it happens before any routing exists. Once an interface runs at hundreds of megabits and the edge rates fall into the picosecond range, the performance of the link is set by the front-end decisions rather than by the software that uses it, and those decisions have to be justified with numbers instead of with habit.

Why Timing Analysis Belongs at the Start

The purpose of timing analysis is to derive the layout constraints from the timing relationships of the devices, rather than to check the layout afterward and hope. It starts from the setup and hold requirements of the receiving device and the clock-to-output delay of the driver, and it ends with a maximum and minimum permissible trace length for each net. That result is what makes a routing rule meaningful. A rule that says a group of nets must be matched to within a certain length is only useful if the number came from a calculation; a rule that came from the previous project may be either too strict or too loose for this one.

Signal Integrity and Timing Are One Problem

Timing cannot be analysed in isolation from signal quality. A reflection on a trace shifts the point in time at which the receiver crosses its threshold, and crosstalk from a neighbouring net does the same. The result is a shift in the effective delay that no simple length calculation predicts. This is why the two are treated together: the quality of the waveform determines whether the assumed timing relationship holds, and a design that meets its length budget but has poor signal quality can still fail at the receiver. Both effects have to be considered before the margins are declared acceptable.

Flight Time and How to Obtain It

Flight time is the difference between the moment a signal leaves the driver and the moment it settles at the receiver, and it captures the delay contributed by the trace and by the load. In a slow design it can be estimated from the trace length and the propagation velocity of the dielectric. In a high-speed design that approximation is not good enough, because the load presented by the receiver and the transmission line behaviour of the trace both modify the delay in ways that a length calculation cannot express. Simulation is used instead, driven by the actual stackup, the actual trace geometry and the actual device models. Once flight time is known for each net, the timing calculation itself can be done with a spreadsheet or even by hand, comparing the arrival time against the setup and hold window of the receiver.

From Timing Budgets Back to Length Rules

Running the calculation in reverse is what produces the routing rules. If the budget allows a certain window at the receiver, then the difference in flight time between the clock and the data is limited, and that limit converts into a length tolerance once the propagation delay per unit length is known. For a matched group, the result is a maximum spread; for a single net, it is a maximum and minimum length. Recording the derivation matters as much as the number, because the next revision or the next project will need to know why the tolerance was set where it was. The technique used to add length where a net is short is described in this article on serpentine routing and length matching.

Common Clock Mode

In a common clock arrangement the transmitter and the receiver are driven from the same clock source, and the data has to arrive at the receiver within one clock period. Two characteristics follow from that. The first is that the clock skew between the two devices matters a great deal, because it shifts the entire window in which the data is valid. The second is that the propagation delay of the data path has to be smaller than the period, which becomes harder as frequency rises. When both the clock and the data are driven by the same type of interface, the calculation reduces to the difference between them, and the physical skew of the two paths is the main variable to control.

When Equal-Length Routing Stops Working

When the clock and the data are driven by different types of output, the situation changes. The two drivers may have different internal delays and different output impedances, so equal physical length no longer produces equal arrival time. In that case the skew has to be adjusted by changing the length deliberately, adding delay to the faster path so that the two arrive together at the receiver. This is the point at which the familiar instruction to route the clock and data to equal length becomes actively misleading, and the calculation rather than the rule has to decide the target. The same reasoning applies to any group whose members are driven differently.

Noise, Intersymbol Interference and Margin

Several remaining effects shift signal phase and are difficult to calculate exactly. Switching noise on the supply changes the threshold of the receiver, intersymbol interference from previous bits moves the crossing point of the current one, and a return path that is not ideal adds an inductive component to the delay. The response is twofold. First, a deliberate margin should be built into the timing budget rather than consumed by the calculation, so that these second-order effects have somewhere to go. Second, the layout measures that reduce them should be applied: continuous return paths under the fast nets, adequate spacing from other traces, and controlled impedance. The coupling mechanisms that most often disturb a timing margin are covered in this article on the 3W rule for crosstalk.

Applying the Result to the Layout

The output of the analysis is a list of constraints, and the layout should be built around them rather than checked against them at the end. The most constrained group is routed first, the reference plane is chosen to support it, and the length targets are applied while the routing is still fluid. Where several groups compete for the same channel, the one with the smallest margin should be given the straightest path. The general approach to bus and high-speed routing that supports this sequence is described in this article on high-frequency traces and data bus routing. Once the board is routed, the actual lengths and the simulated flight times should be extracted and compared against the budget, and any net that exceeds its allowance should be corrected before release rather than waived.

Verifying the Assumptions at Bring-Up

The first prototype is the test of the analysis. Measuring the clock at the receiver, examining the eye diagram of the fastest bus, and checking the timing of the critical setup and hold pair against the calculation will confirm whether the assumptions were sound. Where a measurement disagrees with the prediction, the difference usually points at a modelling assumption rather than at a layout error, and correcting the model is what makes the next design faster to complete. Signing off a design without this comparison leaves the analysis unvalidated, which means the next project starts from the same uncertainty.

FAQ

When does a design need timing analysis? As soon as the interface speed makes the flight time a significant fraction of the clock period, which in practice means most parallel buses and any serial link above a few hundred megabits.

Can equal-length routing replace the calculation? No. Equal length only produces equal arrival time when the two paths are driven identically, and it can be wrong when the drivers differ.

Why is flight time obtained by simulation rather than by length? Because the load and the transmission line behaviour change the delay in a way that a length calculation cannot express, and at high speed the error is large enough to consume the margin.