Signal Integrity Design for Gigabit PCB Interconnects

Gigabit links moved high-speed design out of the laboratory and onto ordinary backplanes and line cards, and with that move the assumptions that had served at lower rates stopped holding. A trace that was previously treated as a wire now behaves as a lossy transmission line, a via that was previously ignored is a discontinuity with its own electrical model, and the power distribution network is expected to hold its voltage through a transient that would have been unthinkable on the previous generation of hardware.

What Changes at Gigabit Rates

At lower speeds, the interconnect could be treated as a connection with a delay. At gigabit rates the amplitude and the shape of the waveform at the receiver depend on the whole channel, and the factors that matter are reflections, ringing, timing, ground bounce and crosstalk acting together. No single one of them is responsible when a link fails to open; the failure is the accumulation of several contributors that each look tolerable in isolation. Signal integrity design therefore has to consider the device, the interconnect topology, the power distribution and the electromagnetic behaviour of the board as one problem rather than four.

Device Models: IBIS and SPICE

Simulation is only as good as the model behind it. Vendors supply models for their devices, but their understanding of a new part evolves, and their published constraints are often conservative to the point of being impractical. The engineer therefore has to evaluate the model rather than accept it, and to use it to refine the topology, the termination scheme and the termination values before deriving the layout rules. Two model types dominate. The IBIS model describes the behaviour at the pins and hides the internal circuit, which is why vendors prefer it and why transistor-level simulation time is avoided. The SPICE model describes the circuit itself and is more accurate in the nonlinear regions, at the cost of simulation time and of exposing information vendors would rather not publish. IBIS is accurate for drivers that operate in their linear region, which is the case for the emitter-coupled and differential families used at these rates; it becomes unreliable when the output stage is driven into saturation, and it cannot represent an active pre-emphasis circuit. By the time rates reach 10 Gbps and the output waveform resembles a sine wave rather than a square wave, a SPICE model is the more appropriate choice.

Loss: Skin Effect and Dielectric Loss

At high frequency the attenuation of a transmission line can no longer be neglected, and the model has to include a series resistance and a parallel conductance. The series resistance has two parts. The first is the ordinary DC resistance of the copper, set by its geometry and resistivity. The second appears as frequency rises, when current crowds toward the surface of the conductor and the effective cross-section shrinks. The depth at which the current density falls to about a third of its surface value is the skin depth, and it decreases as the square root of frequency, so the resistance grows with frequency. The parallel conductance represents dielectric loss, which is negligible at low frequency and becomes dominant as the loss tangent of the laminate takes over. As a rule, conductor loss is the larger contributor below about 1 GHz and dielectric loss dominates above it. Both effects slow the edge and reduce the amplitude, which is why the simulation must be run with a bandwidth consistent with the edge rate of the signal rather than with its clock frequency; a 622 MHz signal and a 2.5 GHz signal may have almost the same rise time. Losing amplitude is not entirely bad, since a slower edge overshoots less, but the loss has to be anticipated in the budget rather than discovered at bring-up.

Crosstalk and Loss Together

Crosstalk depends on the physical structure of the traces, the length over which they run in parallel, the amplitude of the aggressor and the edge rate. Unlike loss, crosstalk does not grow without limit: beyond a certain coupling length it saturates, because the coupled noise from the far end arrives out of phase with the near end. Loss, by contrast, keeps increasing with length. Both effects should therefore be simulated together, because a channel that is short enough to keep crosstalk out of the noise may still be long enough for loss to close the eye.

<img src="https://www.gopcba.com/wp-content/uploads/2026/08/flexible-pcb-assembly-cover.jpg-1.webp" alt="high-speed differential pair routing on a multilayer PCB” />

Via and Connector Models

A via is a controlled-impedance discontinuity: the vertical barrel has no defined impedance, and the transition from a horizontal trace to a vertical one is a break in the path that reflects energy. At gigabit rates the via must be modelled rather than ignored, and the simplest practical via model is a series resistance and inductance with a shunt capacitance, extended to several parallel RLC sections where more accuracy is needed, and eventually to a matrix when coupling to neighbouring conductors is included. Two methods are used to obtain the model: measurement, for example by time-domain reflectometry, and extraction with a three-dimensional field solver from the physical structure. The parameters that drive the result are the material, the stackup, the board thickness, the pad and anti-pad diameters and the way the trace connects to the barrel. Connectors require a similar treatment, and the practical approach is a multi-line model that captures the inductive and capacitive coupling between adjacent pins as a matrix, extracted in three dimensions and delivered as a subcircuit. These models are slow to build and slow to simulate, which is why they are reserved for the nets where the budget is tight.

Differential Signaling and Routing

Differential signaling is used at these rates because it tolerates the effects that would otherwise dominate. Edge-coupled routing and broadside-coupled routing are the two physical options: edge coupling is easier to route and to fabricate and generally produces less crosstalk, while broadside coupling saves routing channels at the cost of tighter process control. Tight coupling improves immunity and reduces crosstalk; loose coupling makes the impedance of the pair easier to hold constant, particularly through a via field. The rule chosen has to balance impedance continuity, loss, crosstalk and skew, and the appropriate figure of merit is the eye diagram, simulated with a pseudo-random bit sequence and with jitter and skew applied as parameters. A pair that meets its impedance target but shows a closed eye under jitter is not a good design. The routing geometry that determines those properties is described in this article on microstrip and stripline routing, and the corner treatment that preserves the pair’s balance is covered in this article on right-angle routing in differential traces.

Power Distribution and EMI

Faster edges mean the supply has to remain stable over a wider band. A board may draw a transient of several amperes while being required to hold its ripple within tens of millivolts, and that requirement is met by the impedance of the distribution network rather than by the regulator alone. The planes, the decoupling capacitors and the way the return current flows all contribute, and the plane structure that keeps the return path continuous is described in this article on power plane splitting rules. The same currents that disturb the supply also radiate, so power integrity and electromagnetic compatibility are addressed together rather than in sequence.

Building the Analysis Into the Flow

The most effective change in method is to move analysis earlier. Modern tools allow rules to be set from simulation and applied during layout, so that a violation is prevented rather than detected. The sequence that works is to fix the stackup and the impedance target, simulate the critical nets for loss, crosstalk and eye quality, derive the length and spacing rules from that simulation, and apply those rules while routing. Checking the finished board against the same models closes the loop, and comparing the first prototype measurement against the prediction tells the team whether the models were sound. Where the measurement disagrees, the model is usually the problem, and correcting it is what makes the following design faster than this one.

FAQ

When is an IBIS model not good enough? When the output stage is operating in saturation or when the device has active pre-emphasis, because the model cannot represent those conditions accurately.

Which loss dominates at 2.5 Gbps? Dielectric loss, as a general rule, since conductor loss dominates below about 1 GHz and the balance shifts toward the laminate above it.

Do vias need to be modelled at gigabit rates? Yes, on any net where the timing or amplitude budget is tight. The barrel is an uncontrolled impedance and the transition reflects energy.