Four-Layer PCB Design: From Schematic Capture to Routing
A four-layer board is the first stackup that gives a designer a real ground plane, and the first where the order of the workflow starts to matter. On a two-layer board the layout can be adjusted almost indefinitely without changing the electrical behaviour very much. Once two inner copper layers are introduced, the return path for every signal becomes a design decision, and decisions taken during setup are expensive to reverse later. Working through the sequence in a disciplined order keeps the board manufacturable and the signal behaviour predictable.
Schematic Capture and Netlist Generation
The design begins with a schematic that is complete enough to generate a clean netlist. In practice this means drawing the symbols, assigning a footprint to every component, and clearing the connectivity warnings before the netlist is exported. Hierarchical sheets help on larger designs because they keep one functional block per page and make the connectivity review tractable. The netlist is the contract between the schematic and the layout: every net, reference designator and pin assignment that the layout tool imports comes from it, so an error that survives into the layout will be reproduced faithfully in copper.
It is worth adding a review step here rather than later. Confirm that power and ground pins are connected, that unused inputs are terminated rather than left floating, and that the schematic notes include any net that needs a special constraint, such as a differential pair or a controlled impedance target.
Board Setup and Layer Planning
Board setup covers the mechanical outline, the stackup and the layer assignment. Fix the outline first, including mounting holes and connector positions, because everything else is placed relative to it. Then define the stackup: on a four-layer board the usual arrangement is a signal layer on top, a ground plane, a power plane, and a signal layer on the bottom. That ordering places both signal layers next to a reference plane, which controls the return path and keeps the impedance of the outer traces stable. Other arrangements are possible and are described in the guidance on layer stackup from one to eight layers.
Layer assignment should be recorded in the design file, not only in a drawing. Naming the planes, defining the dielectric thickness between each pair of layers and setting the copper weight all feed the impedance calculation, and a layout tool that does not know the dielectric thickness cannot report a meaningful trace width.
Design Rules and Parameters
Most default parameter sets are a reasonable starting point: they keep clearances conservative and prevent obvious errors. What should not be left at default are the rules that the fabricator will actually build to. Set the minimum trace width, minimum spacing, minimum annular ring and via sizes to match the fabrication capability being used rather than to the tool default, and set the plane clearance rules so that a via connecting to a plane cannot also short to it through a stale thermal relief.
Net classes are the practical way to do this. Group power nets, high-speed signals and low-speed control lines into separate classes with their own widths and clearances, and apply the impedance rule only to the class that needs it. Constraints applied by class survive later edits; constraints applied by hand do not.
Importing the Netlist and Footprints
The netlist and the footprints are loaded together, and this is the step where layout mistakes are most often introduced. Every footprint must match the physical part: pad pitch, pad size, courtyard and pin numbering. A footprint that is one pin off will route correctly in the tool and fail on the bench, so the import should be followed by a check of the component count and a visual inspection of the unusual parts.
If the schematic has changed since the layout was started, the update has to be applied carefully. Re-importing connectivity without creating new rooms or re-annotating the whole board preserves the existing layout, while a careless update can displace placed parts and invalidate the routing that has already been completed.
Component Placement
Placement is largely manual on a four-layer board, and it deserves the largest share of the layout time. Start with the connectors, the mounting holes and any part whose position is fixed by the enclosure, then place the parts that belong to each functional block together. Follow the signal path from input to output so that the routing has a natural direction, and keep noisy switching blocks away from analogue and sensitive inputs. The general approach is covered in the notes on placement order and pad positioning.
Check the practical details before committing to the placement. Components should be spread evenly so that assembly, insertion and soldering are straightforward, and silkscreen reference designators should be horizontal where possible and never hidden under a part. Polarity marks and pin-one indicators must remain visible after assembly, because they are what the operator uses to verify orientation.
Manual Routing and Inner Copper Layers
Manual routing gives the control that a four-layer board needs. Plan the routing before drawing it: decide which nets run on the top layer, which run on the bottom, and where each signal will change reference. Hide the inner copper layers while routing so that the plane shapes do not obscure the work, and route the critical nets first while the space is still available.
The inner copper layers are usually complete plane shapes rather than routed traces. A pad or via that belongs to the same net connects to the plane automatically at the layer transition, and the connection style and clearance are set by the plane rules. Where a plane has to be split, keep the split away from the region under high-speed traces so that no signal crosses a gap in its return path. Shortening the longest routes by reorganising the placement is usually more effective than adding layers, as discussed in the material on multilayer design rules that shorten the layout.
Working With Two-Sided Assembly
Many four-layer PCB design projects end up with components on both sides, either to save area or to keep a sensitive analogue block away from a switching supply. Two-sided assembly changes the placement plan: the second side has to survive a second reflow pass, so heavy parts belong on the side that is processed last, and any part that cannot tolerate being reflowed twice must be placed accordingly. Adhesive dispensing or a selective soldering process may be needed for large through-hole parts, and both the panel layout and the stencil have to accommodate the two passes without disturbing the parts already attached.
Verification and Output
Before the files are released, run the design rule check and clear every error that is not explicitly waived. Then look at the board as a fabricator would: check the drill table against the stackup, confirm that the solder mask and paste layers align with the copper, and verify that the outline layer closes. Plotting the layers and reviewing them one by one catches problems that the automated check does not report, particularly silkscreen over pads and text that overlaps a component outline.
FAQ
Can a four-layer board be routed automatically? It can, but the result usually needs manual cleanup. Autorouters handle simple digital nets well and struggle with plane connections, controlled impedance and any net with a specific length requirement.
Which layer should the ground plane be on? The layer immediately below the top signal layer is the usual choice, because it gives the top-layer traces the shortest return path. The power plane then sits below the ground plane, so its own noise is shielded from the signal layers.
Is a two-layer prototype a good way to validate a four-layer design? Only for the schematic and the logic. The impedance and the return path behaviour will be different, so measurements taken on a two-layer version do not transfer to the four-layer production board.
