Android Core Board PCB Layout: Routing a Quad-Core Module

An Android core board packs a cellular modem, a quad-core application processor, LPDDR memory, eMMC storage and a power management unit into an area smaller than a business card. The PCB layout for that kind of module is unforgiving, because high-speed memory buses, a sensitive radio front end and several switching regulators all share a few square centimetres of copper.

What the Module Integrates

A typical smart module combines a 64-bit quad-core application processor with 1 GB of LPDDR3, 8 GB of eMMC and a multi-band cellular transceiver covering LTE, WCDMA, TD-SCDMA, EVDO, CDMA2000 and GSM, alongside Wi-Fi, Bluetooth and GNSS.

Because all of those blocks sit on one board, the design cannot treat any of them in isolation. The plan has to assign physical zones, choose the layer stack that separates them, and then hold that separation all the way through routing, shielding and test access.

Stackup and Layer Planning

An eight-layer stackup is the usual starting point: two signal layers on the outside, a solid ground plane, a power plane, and two inner routing layers for the memory bus and the secondary interfaces. The ground planes must be continuous under the memory interface and under the RF section, with no slots crossing either one.

Impedance targets should be defined before routing begins. Single-ended 50 ohm and differential 90 or 100 ohm are typical, and the dielectric thicknesses in the stackup are chosen to hit those values with practical trace widths rather than the other way round.

Placement: RF, Power and Digital Zones

Placement follows the signal path. The antenna and RF front end go at one edge, with the transceiver immediately behind them and a continuous ground reference underneath. The power management block sits at the opposite edge, away from the RF chain and close to the battery or DC input connector.

The processor, memory and storage cluster in the centre. This keeps memory traces short and equal, and it puts the thermal load where the board has the most copper to spread it. Any block that must cross a zone boundary should cross it once, not repeatedly.

DDR Routing

DDR routing is normally the tightest constraint in the design. The address, command and control group should be routed as a single-ended bus with length matching within about 100 mil, referenced to a solid ground plane on the layer directly below.

Data lanes are byte groups: each byte lane plus its data strobe must be matched within a few mils of each other, and the strobe must be routed as a matched differential pair. Keeping all memory traces on one layer, and keeping the via count identical inside each byte lane, matters more than absolute length. For related guidance see blind and buried via stack selection.

Power Delivery

The processor core rail draws several amps at a low voltage, and the transient response is set by the loop area between the regulator, its capacitors and the load. Place the output capacitors as close to the processor pins as the outline allows, and keep the return path directly under the outgoing trace.

Power delivery planning also covers sequencing and decoupling. Each rail needs its own decoupling network, and small capacitors should be placed before large ones when travelling outward from the pin. Splitting the power plane into islands per rail, rather than using one plane for everything, keeps noise from the transmit power amplifier out of the core rail.

EMI Control and Shielding

A cellular module radiates by design, so EMI control focuses on keeping that energy out of the rest of the board. The transmit power amplifier and its supply traces should be routed inside a well-stitched ground enclosure, and the module shield frame should contact ground on all four sides with vias every few millimetres.

Clock and high-speed interface traces need to be kept away from the RF receive path. Where they must run near it, route them on an inner layer between ground planes, and never let them run parallel to a sensitive trace for a long distance. The principles in EMI suppression design principles apply directly here.

Thermal Design

A quad-core processor in a small module easily produces several watts. Thermal vias under the processor ground pad, tied to an internal copper area and to the ground planes, spread that heat across the board instead of concentrating it under the die.

Where the enclosure allows it, a thermal pad on the underside gives the heat an exit path. Even without one, generous copper area on both sides connected by a dense via array lowers the junction temperature enough to affect both reliability and sustained performance.

Secondary Interfaces and Testability

USB, SD card, camera, display and audio interfaces each have their own requirements, but they share one principle: keep differential pairs matched and referenced, and keep the return current continuous across the connector transition. The connector area is where most interface-level EMC problems originate.

Plan test access before layout is frozen. Bringing key power rails, the boot mode pins and the debug UART out to accessible pads costs very little area and turns bring-up from a soldering exercise into a measurement. This is standard practice in a mixed-signal board layout where RF and digital share the same substrate.

Antenna Placement and Board Edge Clearance

Many smart modules use a printed antenna or a chip antenna mounted on the module itself. In both cases the copper under and around the antenna is part of the radiating structure, so the ground plane must stop at a defined distance and the keep-out must be respected on every layer, not only the top one.

Placing the antenna at a board corner, with the ground plane cut back from that corner, gives the most predictable pattern. Placing it in the middle of a long edge couples it to the enclosure and to the user hand, and the resulting detuning is usually worse in the low bands than in the high bands.

Bring-Up and Debug Access

Bring-up on a smart module usually starts with the boot configuration pins, the debug UART and the main power rails. All three should be reachable without removing the shield, either through a small opening in the frame or by bringing the signals to a test pad on the underside.

It is also worth keeping a spare GPIO and a couple of spare pull-up sites on the first build. Most hardware issues found late in a programme are solved by rerouting one signal or changing one resistor value, and having a free pad available is the difference between a five-minute fix and a board respin.

FAQ

Can an Android core board be built on six layers? Six layers works for modules without a full memory bus or with a single-channel interface. Once LPDDR3 at 533 MHz or faster is present, eight layers with two dedicated reference planes is the practical minimum.

How important is it to keep all DDR traces on one layer? Very. Every layer change adds a via stub and a reference transition. Matching lengths across different layers is possible, but the impedance discontinuity is the more likely source of intermittent failures.

Should the module shield be a can or a printed frame? Either works if the ground beneath is continuous and the frame is stitched to it. A stamped can is easier to remove for rework, while a soldered frame gives better electrical continuity and a lower profile.