Power Plane Decoupling to Cut Common-Mode EMI
Most designs treat a decoupling capacitor as the answer to power integrity, and for the first few hundred megahertz that assumption holds. Above that, the capacitor stops behaving like a capacitor and the power distribution network starts behaving like an antenna. The resulting common-mode emi is one of the hardest problems to fix after layout, because by then the plane geometry that caused it is buried inside the stackup.
Where Decoupling Capacitors Stop Working
An IC supply pin needs harmonic current delivered across a wide band, but a capacitor has a finite frequency response determined by its capacitance, its equivalent series inductance and the inductance of the path to the pin. It follows that capacitors cannot supply clean harmonic power across the entire band an IC output demands. Above the self-resonant frequency the part becomes inductive and its impedance rises.
The current that the capacitor cannot supply has to come from somewhere else, and it comes from the power bus. That transient current flowing through the inductance of the bus produces a voltage drop across the decoupling path, and the drop is one of the primary causes of common-mode interference. The problem is therefore not the capacitor value but the impedance of everything between the pin and the plane. Power bus inductance is the variable that layout can still control, because it is fixed by geometry rather than by component selection. Regulator placement interacts directly with that geometry, as described in DC-DC converter layout and routing.
The Power Plane as a High-Frequency Capacitor
Relative to the circuit board the IC sits on, a power layer can be treated as an excellent high-frequency capacitor that recovers some of the energy otherwise lost from discrete parts. A pair of parallel copper planes separated by a thin dielectric stores charge across its whole area, so it supplies current from a distributed source rather than from a single component location.
Because the inductance of a well formed plane pair is very small, the transient voltage that develops across it is also small, and the common-mode component that appears on cables and enclosure surfaces falls with it. Power plane decoupling is therefore a geometry problem: the goal is to make the plane pair the lowest-impedance path over the frequency range where the discrete capacitors have already given up.
What Plane Spacing Actually Buys
How good the plane pair is depends on the hierarchy of the stackup, the material between the layers and the operating frequency, which is itself a function of the IC rise time. A common starting point is a plane spacing of 6 mil in FR-4, which yields an equivalent capacitance of roughly 75 pF per square inch of overlap. Reduce the plane spacing and the capacitance rises in proportion.
That number is small compared with a discrete part, but it is available everywhere at once and virtually no series inductance separates it from the load. For a board of twenty square inches of overlapping power and ground, a 6 mil dielectric pair contributes about 1.5 nF distributed across the whole plane, with the current arriving at the pin through a fraction of a nanohenry.
Rise Time Sets the Requirement
Modern logic leaves very little margin. A device whose output rise time sits in the 100 ps to 300 ps range occupies a substantial share of current designs, and a 300 ps edge is fast enough that a 6 mil plane spacing is no longer sufficient for demanding applications. Extending plane decoupling to that band calls for spacing below 3 mil.
Below roughly 1 mil of dielectric, FR-4 is no longer a practical choice. The layer becomes difficult to laminate at that thickness, and the capacitance still does not reach the target, so a higher permittivity material has to replace it. Ceramic and ceramic-filled polymer dielectrics can meet the requirement for 100 ps to 300 ps edges, at a cost and a process qualification burden that must be planned for rather than added late.
When Standard Materials Are Enough
Not every design needs thin dielectric. For circuits whose rise times are in the nanosecond range, a conventional 6 mil FR-4 plane pair with well placed high frequency decoupling capacitors is usually sufficient to keep the transient low and the common-mode emissions under control. The high-end processors of a decade ago are the mainstream parts of today, and the material choice has to be matched to the edge rates actually present.
A practical stackup for that class of design assumes 3 mil to 6 mil plane spacing, with power and ground assigned to adjacent layers across the whole board wherever possible. Splitting a plane into functions is sometimes unavoidable, but every split forces return current to detour, and the rules for doing it without creating new problems are covered in power plane splitting rules.
Routing from the Plane to the Pin
The plane is only useful if the connection to the IC supply pin is short and low in inductance. Where the pin can be dropped directly to the plane with a via adjacent to the pad, the loop is minimized and the connection is as good as the plane itself. Where the pin must be routed across the board before reaching the plane, that routing inductance re-enters the problem and the plane loses much of its advantage.
Placement therefore drives performance. Decoupling parts should sit on the side of the board closest to the plane they serve, with the shortest possible connection between the pad and the plane, and the plane pair should extend under the whole device footprint rather than stopping at its edge. A package escape that forces a long detour is a stackup problem, not a capacitor problem.
Verifying the Result
The effect of plane decoupling can be measured before the design is released. A field solver applied to the stackup returns the plane capacitance and the spreading inductance, and a simple calculation using the target edge rate shows whether the pair covers the band of interest. Simulation of the complete network, including the discrete parts and their mounting inductance, shows where the transition between the two current sources occurs.
On hardware, the check is a near-field scan of the board surface and a current probe on the attached cables. A structure that is working shows a smooth impedance curve with no high impedance peak in the band of concern, and a cable current that stays flat as the clock harmonics sweep. Ground return design interacts strongly with this, as described in ground current and harmonic distortion.
FAQ
Can plane decoupling replace discrete capacitors? No. The plane pair covers the high frequency end of the band where capacitors have turned inductive, while the discrete parts cover the low frequency end where the plane capacitance is too small to matter. The two work as one network and neither is sufficient alone.
Is thinner dielectric always better? It is better electrically and worse industrially. Thinner cores are harder to laminate, more sensitive to copper imbalance and more expensive, so the thickness should be chosen from the measured or specified edge rate rather than set as low as the process allows.
How many ground vias are needed around a plane pair? Enough that the plane pair behaves as a distributed structure rather than a pair of floating sheets. Stitching vias spaced at a fraction of the shortest wavelength of interest along the board perimeter contain the field and prevent the plane edges from radiating.
