Six-Layer PCB Design Rules and Stack Choices

A six-layer board is the point at which a design stops being constrained and starts being comfortable. Four layers give a ground plane and a power plane, but only two signal layers to route on, and those two layers are often in conflict with the planes sitting between them. Six layers add a second pair of signal layers, and with careful arrangement every signal layer can touch a plane.

This article covers the arrangements that work, the ones that do not, and the design rules that follow from the choice.

Why Six Layers Are Chosen

The usual reason is escape routing. A fine-pitch package with several hundred connections cannot be routed out on two signal layers without an impractical amount of via sharing, and the additional layers give each row of balls its own routing channel. The second reason is power integrity: a six-layer board can dedicate two planes to power and ground, which lowers the supply impedance across the whole board.

The third reason is less obvious and more valuable. With two plane layers, the designer can place a plane adjacent to every signal layer, which means no trace has to be routed with a distant reference. That property, rather than the extra routing area, is what improves signal integrity, and the stack-up design guidance explains how it should be planned.

Arrangements That Work

The standard high-performance arrangement is signal, ground, signal, power, ground, signal. Every signal layer touches a plane, the two ground planes are separated by the power layer, and the power plane sees ground on both sides, which gives the lowest supply impedance of any six-layer stack.

A simpler and cheaper arrangement is signal, ground, signal, signal, power, ground. It uses only two plane layers and puts two signal layers next to each other in the middle. That pair of adjacent signal layers couples strongly to each other, so it should carry only slow signals, and the arrangement should not be used for boards with high-speed interfaces.

Arrangements to Avoid

Placing the power plane near the top and the ground plane near the bottom, with signals between them, produces a stack in which the outer layers have a distant reference and the power plane has high spreading inductance. The result is poor common-mode performance and impedance that varies with what is routed nearby.

The same applies to any stack where a signal layer has no adjacent plane. That layer behaves like a two-layer board for as long as the signal stays on it, so the improvement the extra layers were bought for is not realised. If the layer count is fixed by the routing demand and not by the electrical requirement, at least the critical interfaces should be routed on layers that do have a reference.

Stack Symmetry and Fabrication

A six-layer stack has to be balanced about its centre. The dielectric thicknesses and the copper weights above and below the middle should correspond, or the board will bow during lamination and reflow. Symmetry also keeps the impedance calculation simple, because the same dielectric height appears on both halves of the stack.

The lamination sequence follows from the arrangement. A six-layer board with through vias only needs a single lamination cycle, which keeps the cost and the lead time low. Introducing blind or buried vias requires sequential lamination and changes the cost structure completely, so it should be justified by a routing requirement rather than adopted for convenience. The layer stack reference describes how the arrangements scale as the count increases.

Impedance Control on Six Layers

Six layers make impedance control easier, because a signal layer adjacent to a plane gives a well-defined microstrip or stripline geometry. A 50 ohm microstrip on 0.2 mm of FR-4 is roughly 0.35 mm wide, while the same impedance as a stripline between two planes needs a narrower trace for the same dielectric height.

The calculation has to use the actual stack, and the tolerance on the dielectric thickness determines how well the impedance can be held. Specifying the target impedance with a tolerance and letting the fabricator adjust the artwork is the reliable approach, and the trace width and current calculation gives the geometry for the current-carrying traces on the same stack.

Cost and Layer Count Discipline

Six layers cost more than four, but the increase is smaller than the step from two to four in relative terms, because the setup and the drilling dominate for a simple design. The material cost rises with the layer count and the processing cost rises with each additional lamination cycle, which for a through-via design is still only one.

The discipline is to add layers for a reason that can be stated. Escape routing, plane adjacency and power integrity are all legitimate reasons. Adding a layer because the routing is difficult, without understanding why, usually produces a board that is not much easier to route and considerably more expensive to build.

Decisions to Make Before Routing

The stack arrangement, the dielectric thicknesses, the via scheme and the impedance targets should all be settled before the layout starts. Changing any of them afterwards invalidates the controlled-impedance traces and may change the lamination sequence.

The component placement should also be reviewed against the plane arrangement at the same time. A device placed over a split in a plane loses the benefit of the plane, and on a six-layer board the splits appear where the power plane is divided into separate rails. Planning those divisions with the placement is part of the stack design rather than a routing detail.

Making the Plane Pair Work

Where a six-layer stack includes both a power and a ground plane, those two layers form a plane pair, and the spacing between them determines how much capacitance the pair provides and how low its impedance is. A 6 mil separation on FR-4 gives roughly 75 pF per square inch, and reducing the spacing raises that figure in proportion.

The pair is only useful if it is continuous. Splitting the power plane into separate rails reduces the area of each pair and therefore its capacitance, so the splits should be arranged to keep the largest and noisiest rail adjacent to a full ground plane. Where a rail has to be split, the two halves should still be referenced to the same ground plane rather than to different ones, so that a signal crossing between them has a return path available. Keeping the plane pair close to the devices that draw the most current, and keeping the copper between them free of unnecessary slots, is what turns the extra layers into a measurable improvement rather than a cosmetic one.

FAQ

Is six layers enough for a high-speed design? For most designs it is, provided the interface routing is arranged so that every high-speed net has a continuous reference plane. Boards that need more layers usually need them for routing capacity rather than for electrical reasons.

Should the power plane be split into several rails? Usually yes, but the splits should be planned with the placement, because a trace crossing a split loses its reference. Where a signal must cross, a stitching capacitor at the crossing restores the return path.

Does a six-layer board need blind vias? Only if the routing genuinely cannot close with through vias. Blind and buried vias add lamination cycles, raise the cost substantially and add process risk, so they should be a considered decision rather than a default.