PCB Stack-Up Design Guide for Multilayer Boards

A stack-up is the drawing that fixes how many copper layers a board has, how thick each dielectric is, and which layer carries signals, power or ground. It is written long before the first trace is routed, and almost every later decision depends on it: trace width for a target impedance, via geometry, controlled-impedance tolerance, and the price the fabricator quotes. This is why a multilayer board is designed from the stack outward.

Getting the stack-up right at the start is cheaper than rebuilding it later. The rules below cover what the drawing must contain, how to arrange the layers, and how to keep the board flat and manufacturable.

What a Stack-Up Drawing Actually Defines

A usable PCB stack-up lists, for every layer, the function, the copper weight and the dielectric thickness. It also states the total board thickness, the surface finish and the laminate family. Without the thickness of each dielectric the fabricator cannot build a controlled-impedance board reliably, because impedance depends on the distance from the trace to its reference plane.

The drawing should also record which layers are core and which are prepreg, since the lamination sequence follows from that. A stack-up that cannot be laminated in the stated order is not manufacturable, no matter how elegant the electrical design looks on paper.

Why Layer Arrangement Matters

Every signal layer needs an adjacent reference plane. When a trace is routed on a layer next to a solid plane, its return current flows directly underneath it and the loop area stays small. When the nearest plane is two layers away, the return current has to spread out, the loop area grows, and both radiation and crosstalk increase.

That single rule usually settles the layer arrangement, and it is the reason a layer count review should happen before any net is routed. On a four-layer board the sensible order is signal, ground, power, signal. On a six-layer board, signal, ground, signal, power, ground, signal keeps every signal layer next to a plane while using only two dedicated plane layers.

Board Warpage and Stack Symmetry

Copper and laminate expand at different rates, so an unbalanced stack will bow during reflow. The usual defence is symmetry: keep the total dielectric thickness above and below the centre line equal, use the same copper weight on mirrored layers, and avoid putting a heavy copper plane on one side only.

In an eight-layer board, for example, the thickness between layers two and seven should be similar so the mechanical centre coincides with the geometric centre. Symmetry also helps impedance control, because identical dielectric heights give identical trace widths for the same target impedance. When an odd layer count is unavoidable, the balance rules for odd stacks describe how to recover the symmetry without adding a layer.

Impedance Control Starts With the Drawing

Trace width is an output, not an input. Once the stack-up fixes the dielectric height and the copper thickness, the width needed for 50 ohms, or for a 90 ohm differential pair, is determined. This is why the stack-up has to be frozen before routing begins: changing a dielectric later forces every impedance-controlled trace to be re-tuned.

State the tolerance as well. A common specification is plus or minus ten percent on the target impedance, which the fabricator meets by controlling etch and plating. Tighter tolerances are possible but cost more, and they only help if the connector and the driver are matched to the same target.

Materials and Their Trade-Offs

Standard FR-4 covers the majority of digital boards. It is cheap, flame retardant and available in many thicknesses. Its dielectric constant moves with frequency and with temperature, which is acceptable below a few gigahertz and increasingly awkward above that.

For RF work or very fast digital designs, low-loss laminates and PTFE-based materials offer a flatter dielectric constant and a lower loss tangent. They cost several times more and are harder to process, so the decision should follow from a loss budget rather than from habit.

Layer Count and Cost

Cost does not rise linearly with layer count. It rises in steps, because the fabricator buys laminate in standard thicknesses and because each additional lamination cycle adds a pass through the press. Moving from four to six layers is usually a modest increase; moving from six to eight or ten, or introducing blind and buried vias, is a larger one.

Choose the smallest layer count that satisfies the return-path and routing rules. Adding layers to solve a routing congestion problem is legitimate; adding them because the design feels safer is not, and it delays the project.

Document the Stack for the Fabricator

Send the stack-up as a separate drawing with the Gerber data, and include the controlled-impedance table that names each target and the layer it applies to. Ambiguity here is the most common cause of a board arriving with the wrong dielectric height, which stays invisible until the impedance measurement fails.

Also state the finished thickness tolerance, the surface finish and any requirement for via filling or tenting. When the stack-up, the impedance table and the fabrication notes agree with each other, the quote comes back faster and the first article is more likely to pass.

Via Types Change What the Stack Can Do

A through-hole via passes through every layer, so it consumes pad area on each one and blocks routing on all of them. Blind and buried vias connect only the layers that need connecting, which frees routing space on the layers in between and lets a dense board close on fewer layers than it otherwise would. The price is sequential lamination, additional drilling and plating cycles, and a longer lead time.

Microvias, formed by laser drilling, are typically 0.1 mm in diameter and connect only adjacent layers, which makes them the natural companion of a high-density stack. The stack-up and the via scheme therefore have to be designed together: a stack planned for through-holes cannot simply absorb a buried via pair later, because the lamination order and the dielectric thicknesses change with it. See the blind and buried via selection notes for how the choice interacts with layer count. A practical rule is to use through vias everywhere up to eight layers unless the routing genuinely will not close, then introduce blind vias only between the outer layer and the first inner plane, and reserve microvias for HDI designs where the density justifies the cost.

FAQ

Can a four-layer board be used for high-speed signals? Yes, if the stack is signal, ground, power, signal and the signals stay on the outer layers next to a plane. What a four-layer board cannot do is provide two clean reference planes for traces routed on inner layers, which is where six layers become worthwhile.

How thick should the dielectric under a 50 ohm trace be? There is no single answer, but several common values exist: about 0.2 mm on FR-4 gives a roughly 0.35 mm wide trace, which suits dense routing. Thicker dielectric means a wider trace, lower loss and a bigger board, so the choice follows from the layout density.

What happens if the stack-up is not symmetrical? The board tends to bow during reflow, and the bow can be large enough to interfere with component placement or with a connector. Symmetry is cheap to design in and expensive to correct once the tooling has been made.