Signal Integrity in the PCB Design Flow

Signal integrity is not a property that can be added to a layout at the end. The decisions that decide it, which layer each signal runs on, what it is referenced to, and how far it runs beside its neighbours, are all taken during the placement and the stack-up, long before anyone measures a waveform.

This article follows the sequence in which signal integrity problems are created and prevented, from the edge rates of the devices themselves through stack-up planning to the routing rules that keep the result predictable.

Why the Design Flow Matters More Than the Fix

Signal and power integrity problems are intermittent by nature. A board that works on the bench and fails in the field, or that passes at one temperature and not another, gives almost no information about where the problem is. Finding the cause later means probing a working product.

Building the answer into the flow is cheaper. A stack-up that provides a reference plane under every signal layer, a placement that keeps the fast devices together and a routing that respects the return path produce a design that has margins rather than a design that happens to work. The arrangement of the layer stack is where that begins.

Edge Rates, Not Frequencies

The parameter that drives signal integrity is not the clock frequency but the transition time of the drivers. A signal that changes state in a nanosecond contains energy at frequencies far above its repetition rate, and it is that energy which interacts with the geometry of the interconnect. The repetition rate tells you how often the event happens; the edge tells you how much of the spectrum it contains.

This is why a low-frequency interface on a modern device can behave like a high-speed one. Three decades ago an edge took tens of nanoseconds and the geometry of the board was electrically short in comparison. Devices today switch in around a nanosecond, and the same trace that was transparent then is a transmission line now.

Reflections on Untreated Lines

A trace driven by a fast edge and left unterminated behaves like a transmission line with a mismatched end. The energy that arrives at the receiver reflects back, and the reflection returns to interfere with the incident waveform, producing overshoot, ringing and a delayed threshold crossing.

The remedy is to match the impedance of the line to its driver or its load, either with a series resistor near the source or a termination at the far end. The design decision is which of the two the interface supports, and the number that goes with it comes from the stack-up rather than from the schematic. A termination chosen without reference to the trace impedance reflects as badly as no termination at all.

Crosstalk: Edge Coupling and Broadside Coupling

Crosstalk is the coupling of energy from one trace into another through the electric and magnetic fields around them. It appears as noise on a quiet line, as a change in the delay of an active one, and it grows with the length over which two traces run close together and with the speed of the edges involved.

There are two geometries. Edge coupling happens between traces running side by side on the same layer, and it is the familiar case that spacing rules address. Broadside coupling happens between traces on adjacent layers that run parallel to each other, and it is generally stronger because the traces face each other across a thin dielectric. A spacing rule applied to one layer does not protect against the second case.

Radiation From Fast Edges

The same energy that couples into adjacent traces also radiates. A net that carries a fast edge on an unterminated line produces ringing, and ringing is a high-frequency current that the board and its cables will radiate efficiently. A design that used to pass an emissions limit with the same clock frequency can fail it after a device change that only shortened the edge.

The countermeasures are structural rather than cosmetic. Keeping the return current close to the signal, avoiding the long unterminated stubs that create the ringing in the first place, and providing a continuous reference under every fast net are the measures that matter, and the principles of suppressing emissions describe them in more detail.

Stack-Up Planning: Reference Planes and Dielectric Height

The first decision in a high-speed design is which plane each signal layer will be referenced to. Every signal layer should sit next to an uninterrupted plane, so that the return current has a defined, adjacent path to follow. When the reference is interrupted, the return current has to detour, which enlarges the loop and changes the impedance.

The thickness of the dielectric between a signal layer and its plane is the second control. Reducing that height tightens the coupling between the trace and its return path, which lowers crosstalk and reduces the loop area, and it does so without consuming any board area.

Impedance Targets in a Single Stack

A modern board usually has to support several impedance targets from the same stack: single-ended nets around fifty ohms and differential pairs at a hundred, memory interfaces at lower values, and serial links at ninety. The stack has to be planned so that all of them can be achieved by adjusting trace geometry rather than by changing the layer arrangement.

The plane structure also provides capacitance between the power and ground planes, which lowers the high-frequency impedance of the supply and reduces the noise that appears on it. A tightly coupled pair of planes serving a fast device does part of the decoupling work that discrete capacitors cannot do at the highest frequencies.

Routing Choices That Preserve Integrity

Routing after the stack is fixed is a matter of respecting the rules that were planned. Groups of signals are spaced so that parallel runs are limited, the interval over which two nets run side by side is kept as short as the interface allows, and the return path under each net is checked rather than assumed.

Where a signal has to change layers, the return path changes with it, so a via that carries a signal should be accompanied by a return via unless the planes are the same net. The geometry of the trace itself matters too, and the differences between microstrip and stripline routing explain why the same trace width gives a different result depending on which layer it uses.

FAQ

Do I need to worry about signal integrity on a slow design? Only where the edges are fast. A design built from slow, modern devices with nanosecond edges still has fast edges, so the answer depends on the devices rather than on the clock rate.

Can a board be fixed after it is built? Sometimes, by adding series resistors or terminations to the nets that ring, but the loop area and the reference continuity are fixed in copper. Preventing the problem is a layout decision.

How does a designer know the impedance is right? By having the fabricator confirm the stack and the resulting impedances against the trace geometry, and by keeping the geometry constant along each net rather than changing width to fit routing.