Signal Integrity Problems on PCBs and How to Fix Them

A board that works perfectly at low speed can fail intermittently at high speed without any component being faulty. The reason is signal integrity: the behaviour of the copper itself once the edges of a signal become fast enough to interact with the geometry of the interconnect. Signal integrity problems rarely destroy a product outright. Instead they reduce margin until a batch of boards fails at temperature, or a link that worked in the lab drops out in the field.

What Signal Integrity Actually Measures

Four quantities describe most of what matters. The shape of the waveform at the receiver tells you whether reflections are present. The noise floor tells you how much unwanted energy is coupling in. The timing margin tells you how much of the clock period is left after skew and jitter. And the impedance profile along the route tells you whether the design is doing what the schematic intended.

All four are consequences of geometry rather than of schematics. The same net, routed two different ways on two boards with identical bills of materials, will behave differently. That is why signal integrity work is largely a review of layout rather than a review of the netlist, and why it pays to fix problems in the stackup rather than in firmware.

Reflections and Impedance Discontinuities

Wherever the characteristic impedance of a route changes, part of the signal reflects back toward the driver. The common causes are a change in trace width, a via transition, a connector, or a termination that does not match the line. The reflected energy arrives later than the original edge and either adds to it or subtracts from it, producing the overshoot and ringing that show up on a scope.

Preventing reflections begins with a controlled impedance stackup and a consistent trace geometry. Where the geometry must change, keep the discontinuity short compared with the rise time of the signal. Where a stub cannot be avoided, keep it short, and remember that a single unplanned test point or probe pad can be enough to create a visible reflection on a fast net.

Crosstalk Between Neighbouring Traces

Crosstalk is energy transferred between traces through the electric and magnetic fields that surround them. It grows with parallel length, with closeness and with the speed of the edge. A victim trace shows a narrow spike at the moment the aggressor switches, and the spike can be large enough to cross a logic threshold on a sensitive input.

Three layout habits control most of it. Keep parallel runs short, especially on the same layer. Increase separation, since coupling falls sharply with distance. And provide a return path close to each trace, because a signal whose return current is nearby has less field to share with its neighbours. Routing a ground trace between two sensitive nets is a simple and effective fence, and the same separation logic that governs EMI suppression design principles applies to crosstalk between digital nets as well.

Ground Bounce and the Return Path

Return current follows the path of least impedance, and when a fast signal changes reference planes the return has to find a way across. If the planes are joined only at a distant point, the return loop becomes large and both radiation and ground bounce rise. Ground bounce shows up as a shift in the reference level of a driving device, which changes the apparent threshold of every signal it sends.

A return via beside every signal via keeps that loop small, and a solid ground plane under every fast route keeps the return current directly beneath the trace. Splitting planes to isolate analogue and digital sections is a legitimate technique when done deliberately, as described in power plane splitting rules, but an unintentional split across a fast net is one of the most common causes of inexplicable failures.

Jitter, Skew and Timing Budgets

Skew is the difference in arrival time between two signals that are supposed to be simultaneous, usually caused by different trace lengths. Jitter is the variation of that arrival time from cycle to cycle, caused by noise, crosstalk and supply variation. Together they consume the timing budget that the interface standard leaves for the board.

Matched length routing handles skew, and the required tolerance comes from the interface specification converted into time and then into distance using the propagation velocity of the laminate. Jitter is harder to design away because it has many sources, but clean power delivery, controlled crosstalk and a continuous reference plane remove most of the controllable part. Differential pairs deserve particular attention, since any asymmetry converts part of the differential signal into common mode noise.

Termination Strategies

Termination absorbs energy so that it does not reflect. Series termination at the driver works well for point to point nets with a single receiver, because it damps the edge without drawing static current. Parallel termination at the receiver suits buses and gives a clean waveform at the cost of continuous current, which matters on battery products.

Differential nets can be terminated with a single resistor across the pair, or with a resistor divider when a common mode bias is needed. Place the termination as close to the receiving pin as possible, and keep the stub from the pin to the resistor short, because that stub is itself an impedance discontinuity. The choice of scheme should follow the topology and the standard rather than tradition.

Measurement and Design Checks

Simulation is useful, but measurement closes the argument. A high bandwidth scope with a low inductance probe, or a time domain reflectometer, will show whether the assumptions in the stackup match reality. Measure at the receiver pin rather than at the driver, since that is where the logic decision is made, and use the shortest possible ground return for the probe.

The cheapest intervention remains the design review. Walk each critical net from driver to receiver, confirm the reference plane, the impedance, the termination and the length tolerance, and record the result. Our notes on the PCB design review process describe how to structure that check so it catches problems before fabrication rather than after assembly.

FAQ

Do I need signal integrity analysis for every board? No. Boards whose fastest edges are slow compared with their trace lengths work reliably with ordinary good layout practice. Analysis earns its cost when interfaces run at high speed, when traces are long, when a design has failed an EMC test, or when the product cannot tolerate a respin. A short review of critical nets is usually enough.

What is the single most effective layout fix? Keeping a continuous reference plane under every fast signal. Most reflection, crosstalk and radiation problems are worse when return current has to detour, and a solid plane removes that cause at no cost. Layout discipline on the reference plane does more than any component added later.

How do I choose between series and parallel termination? Look at the topology. A single driver feeding one receiver is usually best served by series termination at the driver, because it is cheap and draws no static current. Buses with multiple loads and stubs generally need parallel or Thevenin termination at the far end to control the waveform. Battery powered designs should account for the static current of parallel schemes.