Display Interface PCB Routing Guide

A display interface is the place where high speed digital design meets a mechanical assembly that the designer does not control. The panel has its own timing, its own connector and its own tolerance for signal quality, and the board has to deliver a defined eye at the far end of a link that includes a flexible cable and a mating connector. The layout is where that margin is won or lost.

What a Display Interface Carries

A modern display link combines one or more high speed data lanes, a clock, a low speed control channel and several power rails for the logic and the backlight. The data rates range from a few hundred megabits per second for a small panel to several gigabits per second per lane for a high resolution one, with the clock embedded in the data stream in the newest standards.

The slow signals deserve attention as well. A reset line that powers up before the panel supply, or a control channel that is polled before the panel is ready, produces a blank screen that looks like a hardware fault. The power up sequence specified by the panel datasheet should be implemented as a controlled sequence rather than as a set of independent pull ups.

Power sequencing is part of the interface specification. Most panels require the logic supply to come up before the driver supply, and some require the reverse order at power down. A board that applies both rails together may work on the bench and fail on a unit whose supply rises slightly faster, which is why the sequence belongs in the design rather than in a note.

Differential Pairs and Impedance Control

Each high speed lane is a differential pair with a specified impedance, commonly 85 or 100 ohms, and the routing has to hold that impedance from the driver to the connector. The stackup, the trace width and the spacing all set the value, and a change in the reference plane changes it as well, which is why a pair routed across a plane split is worse than a pair that is simply longer than ideal.

Skew within a pair converts differential signal into common mode current, which radiates. Length matching to a few tenths of a millimetre is normal practice, and the matching should be done with small adjustments along the route rather than with a single detour at the end, which creates a local impedance discontinuity. The rules are the same as for any high speed link, described in our guide to microstrip and stripline routing.

Inter pair spacing matters for crosstalk between lanes. The three times the trace width rule is a reasonable starting point, and where the pairs must run close for a long distance, the coupling can be reduced by keeping them on different layers or by separating them with a ground trace that is stitched to the plane at intervals.

Display interface connector on a display driver board

Connector Pinout and Return Paths

The connector pinout is often fixed by the panel, but the assignment of ground pins is not. A ground pin next to every high speed pair gives the return current a short path and reduces the loop area of the link, which lowers both the emissions and the crosstalk. Leaving the grounds at the ends of the connector only forces the return current to take a long detour across the whole interface.

Where the connector footprint allows, place the pairs in the order that lets them route straight from the driver without crossing. Crossing pairs on a dense interface forces layer changes, and every layer change adds a via pair whose stub and impedance discontinuity degrade the eye. Planning the escape order carefully during placement saves a week of tuning later.

Ground the connector shell to the chassis or to the board ground through a low impedance connection, and make that decision deliberately. A shell connected to the digital ground can carry the shield current through the logic ground, while one connected to chassis keeps that current out of the board. The choice depends on the enclosure and on whether the panel is referenced to the same ground as the main board.

Flex Cables and Board to Board Links

A flexible cable is part of the transmission line, not an accessory. Its impedance, its length and its connector termination all affect the signal at the panel end, and a cable rated for the data rate is worth the additional cost. A cable that is too long for the data rate produces a link that works at room temperature and fails when the panel warms.

Where the flex cable carries high speed lanes, keep the return path on the adjacent layer of the flex and avoid routing the lanes on the outer layer of a two layer flex without a ground return beside them. A cable with a ground plane is preferable for any link above a few hundred megahertz, and the connector should have a defined contact arrangement for the signal and ground pins.

Mechanical retention matters because a partially seated connector behaves like a cable with excess capacitance and inductance, and the link may work intermittently. Use a connector with a locking mechanism or provide a mechanical clamp, and specify the mating force in the assembly instructions so that the connection is fully seated on every unit.

High speed display interface routing on a PCB

ESD and EMI Radiation Control

The connector is the point where a display link meets the outside world, so it is the place where electrostatic discharge enters the board. Place the protection devices as close to the connector as the layout allows, with a return that goes to the ground plane through a short via rather than a long trace. A protection diode placed a centimetre away lets the discharge travel across the board before it is clamped.

EMI radiation from a display interface is usually dominated by the common mode current on the flex cable, not by the differential signal on the board. A common mode choke at the connector, a well matched pair impedance and a continuous return path together reduce that current. Ferrite beads on the power rails to the panel help as well, because the panel ground can otherwise carry switching noise back into the board.

The clock is the other frequent source. If the clock is a separate single ended line, it behaves as an antenna and should be routed with a return trace beside it and kept as short as possible. Where the clock is embedded in the data, the same rules as the data lanes apply, and the general method for tracing the radiating currents is set out in our article on EMI suppression design.

Measure before adding components. A near field probe moved along the cable shows which part of the link radiates, and a current probe around the cable shows the common mode current directly. Adding a filter to the wrong side of the interface costs board area and may not change the emission at all.

Bring-up and Debugging

Start with the power sequencing and the reset line, because a display that never initialises gives no information about the link. Confirm each rail reaches its nominal value in the specified order, and check the reset timing against the datasheet before spending time on the high speed lanes.

If the panel initialises but the image is unstable, look at the eye at the connector rather than at the driver. Measuring at the driver shows what the source produces; measuring at the connector shows what the link actually delivers, and the difference between the two is the part the layout controls. A probe with a low capacitance tip is essential on these signals.

Where the link works at low resolution and fails at high resolution, the problem is usually a bandwidth limitation rather than a logic error. Check the trace length against the loss budget, confirm the impedance with a time domain reflectometer, and verify that the flex cable is rated for the data rate. Our article on high frequency data bus routing covers the loss and crosstalk budget in more detail.

If the design needs more layers to route the interface properly, that is worth considering early rather than adding vias and stubs to a crowded two layer board. The advantages of a multilayer construction for high speed links are described in multilayer board advantages, and a display interface is one of the cases where the additional plane layers pay for themselves in yield.

FAQ

How long can a display interface run on a PCB? It depends on the data rate and the loss budget of the laminate. At a few hundred megabits per second a link of several centimetres is comfortable, while at several gigabits per second the length has to be controlled and often equalised.

Do I need a shield on the flex cable? Above a few hundred megahertz a ground plane in the cable is strongly preferred. Below that, a well designed pair with a return conductor on each side is usually adequate.

Why does the display flicker when a motor starts? The motor disturbs the ground reference that the panel and the interface share. Check the return path of the panel ground and the routing of the supply rails before adding filtering.

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