Reducing SI/PI Design Iterations On A Wearable Board
A wearable device compresses a radio, a processor and a memory interface into a volume smaller than a matchbox, and the memory bus is usually the part that causes the trouble. The interface runs fast, the supply is shared with everything else, and there is very little room for decoupling. When the result does not meet its eye mask, the cause is rarely one thing.
This article looks at what makes the memory interface on a small board difficult, why it helps to analyse signal integrity and power integrity together, and how to reduce the number of design iterations that the problem demands.
The context is a wrist worn product using an LPDDR4 memory interface, the low power double data rate standard that most such products rely on.
Why A Small Board Is Harder
The constraints interact in a way that larger boards do not force. The supply network has little area for capacitors, so the impedance of the power delivery network rises at the frequencies where the memory interface draws its switching current. The traces are short but narrow, so their resistance matters more than on a wide board. And the ground structure is fragmented by the components on either side, which makes the return path harder to control.
A wearable also has mechanical and thermal limits that shape the stackup. It is thin, which limits the number of layers, and it may flex, which limits the choice of materials. Those constraints are the reason a stackup that works on a laptop cannot simply be scaled down. The board still needs a reference plane close to the interface, and finding room for it is the first design decision.
Synchronous Switching Noise
The specific problem on a parallel memory interface is that many outputs switch at the same instant. The current they draw is not drawn smoothly from the supply; it arrives in a short pulse, and it has to come from somewhere close by. If the decoupling network cannot supply it, the voltage on the supply dips, and the dip is shared with every other circuit connected to that rail.
That mechanism is synchronous switching noise, and it is where signal integrity and power integrity stop being separable. The noise appears on the supply, so it looks like a power problem, but it is generated by the simultaneous switching of signals, so its magnitude depends on the timing of the data pattern. Reducing it requires changes to the layout of the signals and to the design of the supply network, and a change to either one alters the result.
Why Separate Analysis Costs Iterations
Analysing the two in sequence is the traditional SI/PI workflow. The power network is designed to a target impedance, the signals are routed to their rules, and each is verified on its own. The difficulty is that the interaction between them is exactly the part that is not checked. A supply network that meets its target when the load is a smooth current can still fail when the load is a burst of switching current, and a bus that meets its eye mask on a clean supply can fail when the supply has noise on it.
The consequence is a loop of iterations. The signal analysis passes, the power analysis passes, the board is built, the measurement fails, and the layout is changed without a clear idea of which change addressed the problem. Each pass costs a respin. Treating the two as one analysis, with the switching current from the interface as an input to the supply model and the resulting supply noise as an input to the signal model, breaks the loop because it identifies the mechanism rather than the symptom.
What A Joint Analysis Has To Include
The model has to contain the whole path, not just the board. That starts with the memory package and the controller package, because the inductance of the package is often the dominant term in the path from the die to the decoupling capacitor. It continues through the vias and the plane structure of the board, and it ends at the capacitors, whose placement and connection inductance matter more than their nominal value. The voltage regulator has to be represented as well, at least in simplified form, because it sets the low frequency behaviour of the network.
The boundary conditions are part of the model too. The supply current waveform of the interface is what drives the noise, and it depends on the data pattern, so it has to be defined rather than assumed. Where the interface has a programmable drive strength and slew rate, those settings are part of the analysis, because a slower edge reduces the noise at the cost of timing margin. The strategy for planning the ground and power structure follows from what the model shows.
Cutting The Number Of Iterations
Most of the saving comes from moving the analysis earlier. A feasibility study before layout, using the stackup that is actually available and a reasonable estimate of the decoupling that fits, tells the team whether the interface can meet its target on this board at all. That is cheaper than discovering the limit after the layout is finished.
Two other habits help. Building reusable models of the packages and of the decoupling structures means each new project starts from something verified rather than from a blank sheet. And keeping the decoupling study separate from the routing study means a change to one does not invalidate the other, which shortens the loop when a fix is needed. The layer structure of the board is the constraint that both depend on, so it should be settled before either begins.
Verification Against Measurement
The model is only worth having if it predicts something that can be measured. On the bench, the supply noise at the memory can be measured with a wideband probe and a careful ground connection, and the eye diagram at the receiver can be captured with a pattern that stresses the interface. Comparing those two against the model results tells the team whether the model is trustworthy, and a model that has been correlated once is far more useful on the next project.
Where the measurement disagrees with the model, the usual causes are an incomplete representation of the package, a decoupling network whose mounted inductance is higher than assumed, or a return path on the board that was not modelled. Each of those is a specific thing to fix rather than a reason to iterate blindly. gopcb builds boards for wearable and portable products with controlled impedance and defined plane structures, and confirms the stackup against the simulation rather than leaving the assumption untested. The suppression of emissions from the same interface benefits from the same work, since the noise that fails the eye mask is also the noise that radiates.
FAQ
Is power integrity harder than signal integrity? Neither is harder in principle. The difficulty is that on a small board they interact, so neither can be solved completely on its own.
How many decoupling capacitors does a memory interface need? There is no fixed number. What matters is the impedance of the network across the band, which depends on the placement and the mounting inductance as much as on the capacitance.
Can the interface be slowed down to fix a marginal design? Reducing the drive strength or the slew rate lowers the switching noise and the emissions, at the cost of timing margin and possibly of data rate.
