ICT Test Coverage Design For Board Assembly

ICT test coverage is the fraction of the components and nets on an assembly that an in circuit test can actually reach and verify. It is decided long before the fixture is built, because the access is created in the layout, and a design that omits a test point cannot be recovered later without adding cost to every board that is built.

This article describes what in circuit test measures, how test points are added, how coverage is counted, and where the method stops being economical.

What In Circuit Test Measures

An in circuit test drives a node through a probe and looks at the response at another probe. With the power off it measures resistance between nodes, which detects opens, shorts and wrong or missing parts. With the assembly powered and the device pins held in a safe state, it can measure voltages and check that an oscillator runs, a regulator settles or a memory device responds. The method works because the probes contact the board directly, so a measurement is made on the physical net rather than through the functional path of the product.

The distinction from functional test matters when planning coverage. A functional test proves that the product works as a system but can pass a marginal solder joint that has not yet opened. An in circuit test finds the marginal joint by measuring its resistance, and it also separates a manufacturing fault from a design fault, which is what makes it valuable in a repair loop rather than only at the end of the line. Its place in the wider sequence is described under the PCBA development process.

Adding Test Points In Layout

Every net that will be probed needs a landing area that a probe can reach from the bottom side, and every component that will be measured needs its two nodes brought out. Test points are placed as a grid so that the fixture can be drilled on standard pitch, and they are kept clear of tall parts, connectors and areas that will be covered by a shield or a heat sink. A probe that lands on a pad rather than a dedicated point is acceptable for some measurements and risky for others, because the probe damages the surface and can disturb a joint.

The practical rule is that test points are placed while the layout is being routed, not added afterwards. A net that is buried between two planes has no accessible surface, and a via that is tented or plugged cannot be probed. Where access is genuinely impossible, the design either accepts a reduction in coverage or provides an alternative such as a boundary scan chain. Access requirements belong with the general rules under design guidelines for manufacturability.

<img src="https://www.gopcba.com/wp-content/uploads/2026/08/iStock-1307839840-jpg-1.webp" alt="Bed of nails fixture aligned to board test points” />

The Fixture And Its Limits

The fixture carries a bed of nails arranged to match the test points, and its cost and its limit are both set by the number and the density of those points. More probes mean more wiring, more channels and a stiffer plate, and probing force grows with the number of nails, so the board must be able to take the total load without flexing enough to crack a joint elsewhere. Very small test points require fine probes, which have shorter life and a smaller tolerance for misalignment.

Mechanical limits appear as the board gets denser. Probe pitch below one millimetre becomes difficult to achieve and maintain, and the area behind a fine pitch device or under a module may have no room for points at all. Where a net cannot be probed mechanically, a boundary scan device can drive and sense its own pins through the test access port, which recovers some coverage without probes. The routing that brings those nets out to accessible locations follows the same logic as escape routing and fanout.

Measuring Coverage

Coverage is normally expressed as the percentage of nets and of component pins that are probed, with the numbers reported separately because they answer different questions. A net count tells you how much of the interconnect can be checked, while a pin count tells you how many device pins can be verified individually. A board may probe ninety five percent of its nets while leaving an entire fine pitch device unprobed, and the net figure alone would hide that.

Fault spectrum analysis goes further and estimates which classes of defect the test can actually detect. It counts opens, shorts, missing parts, wrong parts and reversed parts, and reports the fraction of each class that the existing access would find. This is more useful than a raw percentage because a test that probes many nets of the same short length may still miss the defects that matter. Applying the method at the design stage is part of the wider question of how layout decisions affect production.

Where Test Stops Being Economical

In circuit test is economical when the assembly volume is high, the board is small enough to fit a fixture, and the defects it catches would be expensive downstream. It becomes hard to justify when the volume is low, when the fixture cost exceeds the value of the boards, or when the board is so large and dense that the fixture cannot be built at the required pitch. In those cases the test is replaced by a combination of automated optical inspection, X-ray and functional test.

The comparison should be made on the cost of an escaped defect rather than on the cost of the test. A product where a single failure in the field triggers a service call justifies coverage that a consumer accessory cannot support, and the same board tested at two different volumes can justify two different strategies. Making that trade explicit at the start of a programme is cheaper than discovering it after the fixture has been ordered.

Designing For Test From The Start

The cheapest way to raise coverage is to reserve the space before routing begins. A row of test points along the edge, a consistent grid pitch, and a keep-out under a module all cost almost nothing at layout time and are impossible to add later. The electrical rules that make a test point usable, such as a minimum pad size and a clear path for the probe, are the same ones that make a pad reliable for assembly, so the two requirements rarely conflict.

The design review should include the test engineer as a participant rather than as a reviewer of a finished layout. A question asked while the stackup is still open, about whether a net can be brought to the surface on the bottom side, saves a redesign later. Every net that is probed is a net whose solder joints are verified, and that verification is only available if the access was planned when the routing was planned.

Additional Considerations for This Build

Practical attention to opens and shorts pays for itself here, because it decides whether the finished board behaves as the drawing intended. Where the requirement is not stated on the fabrication drawing or in the assembly notes, the shop has to assume a default, and that default is rarely the value the design was simulated with. Stating opens and shorts explicitly, together with the tolerance that applies, removes the assumption and keeps the result predictable from batch to batch.

FAQ

Can a via be used as a test point? A via with an open, untented pad can be probed, and doing so saves space. A tented, plugged or filled via cannot, and the probe damages the surface of the ones that can be reached, so dedicated points are preferred wherever the layout allows them.

How much coverage is enough? It depends on the value of an escaped defect and on the other tests in the flow. Rather than aiming at a fixed percentage, compare the fault classes that would remain undetected against the cost of a failure in the field.

Does adding test points cost board area? It does, but usually less than expected, because a test point can be placed on a net that already needs a via and can share the space around it. The real cost is the keep-out under tall parts, which has to be reserved early.