GPU Power Delivery PCB: From 300 Watts to 2300 Watts
A GPU power delivery PCB has moved from a modest power distribution task to one of the hardest problems on a server board. Industry reporting in August 2026 described accelerator power rising from about three hundred watts in the Volta generation, through four hundred for A100 and seven hundred for H100, toward figures around two thousand three hundred watts for the newest generation, with full liquid cooling and rack power above two hundred kilowatts. The board underneath has to deliver all of it.
The change is not simply more current. Voltage has fallen as current has risen, so the acceptable absolute drop becomes smaller while the current to be carried becomes larger, and both trends push the power distribution network toward a design problem rather than a routing detail.
Why Voltage Drop Governs Everything
If a package draws two thousand watts at a core voltage near one volt, the current approaches two thousand amperes. At that current, a resistance of a tenth of a milliohm produces a two hundred millivolt drop, which is a large fraction of the regulation window.
Every element in the path contributes: copper planes, vias, connector interfaces, and the package itself. The design objective is not to minimise resistance in one place but to keep the total drop across the whole path inside the window under the worst case load step, which is why power integrity analysis is now a primary design activity rather than a check performed at the end.
Copper Strategy
Thick copper reduces resistance but conflicts with fine line routing on the same layers, and it increases board weight and reduces the precision achievable during etching. Designs therefore separate power and signal regions, using heavy copper where current flows and finer copper where routing density is required.
Embedded copper takes the idea further by placing thick conductors inside the board rather than on its surface, providing cross section without consuming outer layers. Designs that use it gain current capacity and thermal spreading at the cost of a more demanding fabrication process, and the choice is usually made with a manufacturer that has run the structure before.
Thermal Coupling Between Power and Signal
Power conversion components dissipate heat next to the processors and interfaces they serve, and in a fanless liquid cooled tray there is very little convection to remove it. Heat therefore has to conduct into the board and outward to a cold plate or a frame.
The consequence is that the same copper carrying current also carries heat, and the thermal and electrical designs cannot be separated. Placing a regulator far from the load reduces thermal coupling but increases the path resistance, so the compromise is found by modelling both effects together rather than optimising either alone.
Decoupling and Its Physical Limits
Capacitors only help if they are close enough that the inductance between them and the die does not dominate their response at high frequency. As currents rise, the physical distance becomes the limiting factor, and the solution is to place capacitors directly beneath the package using microvias for the shortest possible path.
This is one of the reasons advanced HDI techniques have entered server boards that were previously conventional multilayer constructions. It also makes the stack up and via structure part of the power design rather than only part of the signal routing, and it means a change to the stack up can affect power integrity as much as signal integrity.
Materials at Elevated Temperature
Boards operating in a warm liquid cooled environment and carrying high current sit at elevated temperature for long periods. Dielectric materials must retain their electrical and mechanical properties over that time, which puts emphasis on glass transition temperature and on long term stability rather than on initial measurements.
Copper behaviour matters as well, since resistance rises with temperature and reduces the margin the design was built around. Thermal models therefore have to iterate between temperature rise and electrical loss, and the final design is verified by measurement under load rather than by calculation alone.
Layer Counts Rise on Both Sides
The signal side of an accelerator board has moved from sixteen layers to thirty or forty in current designs, with frontier applications discussing structures approaching eighty layers. The power side drives layer count too, because current distribution needs planes and because thermal spreading needs copper area.
Neither requirement can be met by simply adding layers without consequence. More layers mean more lamination cycles, tighter registration and higher cost, so designers balance plane count against copper thickness and accept that the resulting stack is a compromise between electrical performance, thermal performance and manufacturability.
Connectors, Busbars and the Rack Interface
At these currents, the interface between the board and the system becomes a design element. Busbars carry current from the shelf to the board, connectors must have low contact resistance and be rated for the current and for repeated mating, and the mechanical design has to prevent the connection from loosening under thermal cycling.
Voltage sensing at the point of load matters here, because regulation has to account for the drop between the converter and the die. Designs that sense remotely typically need dedicated sense traces routed as a pair to the load, and their layout is as important as the power conductors themselves.
Design Rules That Keep the Board Buildable
Power boards fail in production for predictable reasons: heavy copper that etches unevenly, large plane areas that create lamination pressure differences, and thermal relief that leaves insufficient copper around plated holes. Each of these is avoidable with design rules that reflect the process.
Balanced copper distribution across layers reduces warpage, adequate spacing between heavy copper features prevents etching problems, and via design that accounts for plating capability avoids barrel defects. These rules are usually established with the fabricator, and they are the practical content of design for manufacturing on a high current board.
Testing Under Load
A power board cannot be verified with continuity checks. Functional testing has to apply load, measure voltage at the point of delivery and observe temperature, and it should reproduce the transient conditions the product will see rather than only steady state operation.
Board level test structures help by allowing resistance and thermal measurements on coupons from the same panel, which connects the production process to the performance measured on the assembly. Combining both gives the evidence needed to ship boards into expensive systems, and it is where assembly testing contributes most directly to reliability.
What to Look For in a Supplier
Capability on this class of product is defined by heavy copper processing, thick board lamination, high layer count control and the ability to deliver consistent impedance on the signal layers in the same stack. Asking about the heaviest copper in routine production is more informative than asking about maximum layer count.
Thermal and mechanical capability matter too, since a board that warps during assembly can damage joints on a package that cannot be reworked. Suppliers who build demanding boards routinely will describe how they control flatness and copper balance, which is the practical evidence of capability at these power levels.
Chiplet Packages and Local Conversion
As packages are assembled from multiple dies, power delivery becomes spatially distributed. Different dies may require different rails, and the conversion hardware has to sit near the load it serves while remaining cool enough to function.
That pushes converters onto the board close to the package, sometimes beneath it, which changes the mechanical and thermal layout. Designs that treat power conversion as a centralised function on a separate board find the path resistance and inductance unacceptable at these currents, so distribution and conversion move closer together.
Mechanical Load and Board Stiffness
Heavy heatsinks, cold plates and busbars load the board mechanically, and thick high layer count boards are heavy themselves. Flatness during assembly matters because a warped board can prevent proper reflow of a large package with thousands of joints.
Designers manage this with balanced copper distribution, symmetric stack ups where possible, and mechanical support placed where load is applied. Manufacturers contribute by controlling lamination parameters and measuring flatness on production panels, one of the process details that separates suppliers on this class of product.
What Buyers Should Ask
For power boards the useful questions are specific. What is the heaviest copper weight in routine production, what flatness can be held on a board this size, how is impedance verified on the signal layers of the same stack, and what is the measured drop across a representative board under load.
Answers to those questions describe a manufacturing process rather than a catalogue. They also reveal whether the supplier has built boards combining heavy copper with fine line routing, which is the combination this application actually requires.
Where the Trend Leads
Power per package will keep rising while supply voltages stay low, so current density will continue to increase. That will push more designs toward embedding copper, placing conversion closer to the load and using liquid cooling as the default rather than the option.
For board manufacturers the implication is that the power distribution network is now a differentiator rather than a supporting feature. Companies able to fabricate heavy copper with tight control, and to deliver consistent behaviour across a large panel, will be the ones building the boards that sit underneath the next generation of accelerators, which is a capability question as much as a process question.
