AI Server PCB Fabrication: Layer Count, Materials and Thermal Load
An AI server PCB is one of the more demanding boards in ordinary production, and the difficulty does not come from any single feature. It comes from the combination: a large number of layers, a very high speed interface count, a substantial current delivery requirement and a thermal load concentrated in a small area. Each of those is manageable on its own. Together they constrain the stack-up, the material, the copper distribution and the mechanical construction at the same time, and the decisions have to be taken before the layout begins rather than reconciled afterwards.
The Layer Count and the Stack-Up
A board carrying several accelerator devices and their memory has to route a large number of high speed differential pairs from the devices to the connectors, and those pairs occupy layers of their own. High layer count constructions in the range of twenty to thirty layers are common for this class of product, and the stack-up is designed as a system rather than assembled from a preferred sequence.
The stack-up has to deliver three things at once. It has to provide a controlled impedance for every high speed net; it has to provide a low impedance power distribution with enough copper to carry the current without an unacceptable rise; and it has to keep the return paths continuous for the signals above them. Those three requirements interact, because changing a dielectric thickness to hit an impedance target also changes the spacing available for the power planes, and the copper weight that improves the power distribution changes the etch resolution available for the signal layers.
The result is that a stack-up for this class of board is normally specified with the backplane and the daughter cards in mind, and the passive channel behaviour of the connector and the via transitions is considered as part of the design rather than as a fabrication detail.
<img src="https://www.gopcba.com/wp-content/uploads/2024/09/1-5.jpg" alt="high layer count PCB fabricated for an AI server board” />
Materials and Signal Integrity
The laminate is chosen from the loss requirement rather than from habit. At the data rates used by modern accelerators, the dielectric loss of the material becomes a significant part of the total channel loss, and a standard grade that was perfectly adequate for a slower interface will consume the margin that the link requires. A low loss or ultra low loss material reduces that contribution, at a higher cost and with a different drilling and lamination behaviour.
The signal integrity work continues into the geometry. The trace width and the spacing are set by the impedance target and by the routing density, the via stubs are managed by back drilling or by a blind via arrangement, and the fibre weave orientation of the laminate is considered for the differential pairs where the skew between the two halves of a pair matters. None of those is a fabrication preference; each of them is a consequence of the link budget.
The measurement that closes the loop is performed on the finished board. A test coupon travels with the panel and the impedance of the controlled structures is measured and reported, so that the board in the customer’s hand can be compared with the value the design assumed.
Thermal Management and the Power Delivery
The thermal management of a board of this kind is a structural problem rather than a component problem. A device that dissipates a large amount of power in a small footprint has to deliver that heat into the board and out of it, and the path available is the copper beneath the device, the thermal vias through the board and the plane or the heat sink on the other side.
The copper distribution therefore serves two purposes at once. The plane that carries the current also carries the heat, and a design that has been optimised for current alone may still have a thermal path that is too narrow at the point where the device sits. The current carrying requirement sets a minimum copper thickness, and the thermal requirement sets the area over which that copper has to be available.
The mechanical consequences follow. A heavy copper construction and a large stack-up produce a board that is thicker and stiffer than an ordinary one, and the assembly process has to accommodate that: the reflow profile for a board with a large thermal mass is different from one for a thin board, the panel support during printing matters more, and the board is less tolerant of being flexed during handling and test.
<img src="https://www.gopcba.com/wp-content/uploads/2024/09/Through-Hole-PCB-Assembly2.png" alt="inspection of a multilayer backplane before assembly” />
Where the Fabrication Gets Difficult
The fabrication challenges appear at the points where several of the requirements meet. A high layer count board with a heavy copper inner layer has a drill aspect ratio that has to be plated reliably, which constrains the drill diameter and therefore the via count that the layout can use. A back drilled via has to be drilled twice to different depths, and the depth control is a toleranced operation. A blind and buried via arrangement adds lamination cycles and registration steps.
The registration tolerance across the stack is the consequence of all of it. Each lamination cycle adds an alignment step, and the accumulated tolerance at the outer layers of a twenty layer stack is what determines the annular ring available on the smallest via. That is why the design rules for this class of board are developed together with the fabricator rather than taken from a general table.
Review Before the Layout Is Committed
The most valuable point at which to review an AI server design is before the layout is committed, because that is where the stack-up, the material, the via strategy and the copper distribution can all still be changed. A review that happens after the artwork is released can confirm that the board is buildable; it cannot recover the margin that was lost in the choices that were already made.
The review covers the signal and the power together, since a decision that improves one can degrade the other. It also covers the fabrication consequences, because a design that is electrically elegant but requires a process at the edge of its capability will produce a low yield and a long schedule. Our PCB design and layout team supports this work, the fabrication is handled under PCB manufacturing and the capability limits are stated on the PCB capabilities page, with the assembly following through SMT assembly and the testing under PCBA testing. The records are held with quality management.
Assembly Consequences of the Design
A board of this class is not an easy assembly, and the difficulties follow from the fabrication choices. The panel is thicker and stiffer than the lines usually handle, which changes the support needed during printing and the way the board behaves in the reflow oven. The thermal mass is large, so the profile has to be measured rather than inherited, and the soak has to be long enough for the whole board to reach temperature rather than only its surface.
The components themselves add constraints. A large accelerator package requires a stencil designed for its thermal pad, a placement setting that recognises its ball pattern and an X-ray programme that examines the array after reflow. Where the board also carries a heavy copper inner layer, the paste release and the heat distribution both change, and the settings that worked on the previous revision do not necessarily transfer.
The handling requirements are stricter as well. A thick, heavy board with a large device mounted on it is more susceptible to flex damage during test and packing, and the fixture has to support the board rather than rely on its stiffness. Where the assembly is a backplane, the mechanical support during the connector insertion and removal is part of the product design rather than of the process.
FAQ
How many layers does an AI server board need? It follows from the number of high speed nets and the power distribution, and twenty to thirty layers is common for a board with several accelerator devices.
Why does the material matter so much? Because the dielectric loss becomes a significant part of the channel loss at high data rates, and a lossier material consumes the link margin.
What is the main fabrication limit? The drill aspect ratio and the accumulated registration tolerance across a tall stack, which together set the smallest usable via and the annular ring.
