Designing Hardware Boards Around a Mobile Applications Processor

A mobile applications processor is a system on a chip with everything dense about board design in one package. It has multiple power domains that must come up in a defined order, high speed interfaces that behave like transmission lines, a memory bus that eats routing layers, and a thermal density that a small package cannot spread by itself. Designing a board around one is mostly a matter of respecting those constraints rather than inventing anything.

Starting From the Reference Design

The silicon vendor publishes a reference design that has been validated, and it is the correct starting point. It carries the power sequencing, the decoupling arrangement and the interface routing that the device expects, and departing from it without understanding why is the most common way to create a problem that is difficult to diagnose.

That does not mean copying it blindly. The reference design is usually a compromise made for a particular set of peripherals and a particular board size. What it provides is a baseline that works, from which changes can be made deliberately and tested individually rather than all at once.

Power Integrity and Sequencing

The processor has several supply rails at different voltages, each with its own current profile and its own tolerance. Sequencing matters because applying a rail out of order can forward bias a junction inside the device and damage it, which is why the enable order is specified rather than left to chance.

Decoupling is the other half. The capacitors close to the ball grid array supply the high frequency current that the device demands during a switching event, and their placement matters more than their total value. A capacitor two millimetres away has an inductance that the device sees as a delay, which is why the array is designed as a distributed network rather than a bulk reservoir.

High Speed Interfaces

Modern processors expose interfaces whose rise times make short traces behave like transmission lines. The design rules that follow are the usual ones: controlled impedance, matched lengths within a bus, and a continuous reference plane beneath every trace.

The hard part is not the rule but the congestion. A display interface, a camera interface and a memory bus all want to reach the processor, and the routing space between the ball grid array and the connectors is limited. Escape routing from a fine pitch array usually sets the layer count, and the layer count is decided early. Our layer assignment article covers the structural choices that follow.

Memory Bus Routing

The memory interface is the most demanding block on the board. It is wide, it is fast, and its timing margin depends on every trace in the group having a similar length and a similar propagation delay.

Routing it usually consumes several layers, and the order in which the byte lanes are assigned has a large effect on how easily the escape can be completed. Getting the topology right on paper, before the layout begins, saves the rework that would otherwise be needed when a lane cannot be completed at the required length. The impedance implications are described in our transmission line notes.

Thermal Spreading

A processor dissipating several watts in a package the size of a fingernail cannot lose that heat to the air from the package alone. The board becomes the heatsink, and the copper under and around the device is part of the thermal design.

Thermal vias carry heat to internal planes, which spread it laterally across the board. Where the product has an enclosure, the path from the plane to the case matters as much as the path from the device to the plane, and a design that ignores the second half will overheat despite a well designed first half.

Power Delivery Network

The regulator, the inductor and the bulk capacitance form the supply, and the impedance of the whole network across frequency is what determines how much the rail moves when the processor changes its current demand.

Placing the regulator close to the device reduces the loop area and the parasitic inductance. Where the layout forces the regulator to sit some distance away, the loss has to be compensated with additional capacitance near the load, and the compensation should be calculated rather than assumed.

Debug Access and Bring Up

The first prototype will need to be debugged, and that requires access that is easy to omit when the layout is tight. A serial debug header, a reset button and access to the power rails are worth the board area they consume.

Test points on the critical rails let the bring up be measured rather than guessed at. A board that cannot be probed turns every fault into an exercise in speculation, and the time lost is far greater than the area the test points would have used. Our prototyping article lists the other checks worth making before the order is released.

Selecting the Stackup

The stackup follows from the impedance targets and the escape routing, and both are known before the layout begins. Once the target impedance and the number of routing layers are fixed, the dielectric thicknesses are determined rather than chosen.

Copper weight interacts with the same decision, because the width needed for a given impedance depends on the thickness of the conductor. A design that changes copper weight late in the process has to revisit every impedance controlled trace, which is why the choice belongs with the stackup. Our copper thickness notes describe the trade-offs.

Component Sourcing and Longevity

An applications processor usually has a long but finite life, and the memory and power devices around it have their own. Building a product around parts that will be unavailable in two years creates a redesign rather than a supply problem.

Checking lifecycle status when the design is frozen, and recording the approved alternatives, is what makes a second build possible without re-engineering. The same discipline applies to the passive components, as described in our component tolerance and reliability article.

Interface Protection and Level Shifting

Not every peripheral runs at the processor supply voltage. Level shifting is needed where a device operates at a different rail, and the translation must be fast enough not to distort the signal.

The interfaces that leave the board also need protection against the outside world. ESD protection diodes belong close to the connector so that the transient is diverted before it travels into the board, and the protection component should be chosen for the interface speed rather than for its clamping voltage alone. Our electrical test notes describe how the resulting board is verified.

FAQ

Can the reference design layout be reused directly? The electrical intent can, and often should. The physical layout usually cannot, because the board size, connector placement and enclosure differ.

How many layers does an applications processor board need? It depends on the interfaces, but the escape from the ball grid array and the memory bus normally set a floor of six to eight layers.

Is a heatsink always required? Not if the board and the enclosure can carry the heat away. The thermal path should be designed and then measured on the first prototype.